Contents
Features........................................................... 1
Applications...................................................... 1
Pin Assignment ................................................ 1
Block Diagram.................................................. 1
Terminal Description ........................................ 2
Mode Table ...................................................... 2
Absolute Maximum Ratings ............................. 2
Recommended Operating Conditions.............. 2
DC Electrical Characteristics ........................... 3
AC Electrical Characteristics............................ 3
Read Mode Operation...................................... 4
Counter Hold Mode Operation ......................... 4
Program Mode Operation ................................ 5
Input Priority ..................................................... 6
Notes................................................................ 6
Dimensions ...................................................... 7
Characteristics ................................................. 8
64-bit FUSE ROM
S-2100R
The S-2100R is a CMOS 64-bit serial FUSE ROM. It has a low standby
current (0.3
µA
max., V
DD
=1.5 V) and has a wide operating voltage
range. Data can be read serially by clock pulses from address 1 to
address 64. All the addresses are initialized at “H” so writing into “L”
can be done only once.
Features
•
•
Low standby current (0.3
µA
max., V
DD
=1.5 V)
Wide operating voltage range
Applications
•
•
•
Pager ID ROM
Cordless telephone
Security equipment
Pin Assignment
8-pin DIP
Top view
DATA
CE/PE
COUNTER
OUT
V
SS
1
8
V
DD
DATA
RST
CE/PE
CLK
PD/V
PP
COUNTER
OUT
V
SS
1
2
3
4
8-pin SOP
Top view
8
7
6
5
V
DD
RST
CLK
PD/V
PP
2
7
3
6
4
5
Figure 1
Block Diagram
COUNTER
OUT
DEN
COUT
CLK
CLK
6-BIT
COUNTER
READ / RST
WRITE
CONTROL
VPE
DIN
DOUT
A1
A0
A2
A3
A4
A5
ROW
DECODER
RST
64-BIT
FUSE ROM
MEMORY
CELL
MATRIX
CE/PE
SENSE
AMP.
COLUMN
DECODER
V
PP
V
PP
CONTROL
DATA
DATA
CONTROL
VPIN
V
V
PD/V
PP
DD
SS
Figure 2
Seiko Instruments Inc.
1
64-bit FUSE ROM
S-2100R
Terminal Description
Table 1
Pin No.
1
2
3
4
5
Symbol
DATA
CE/PE
Pin Name
Data input/output terminal
Mode select terminal
Description
Tri-state data input/output terminal
Mode select terminal
(Refer to operation mode table)
6-bit counter; 64th bit detection output terminal
Normally, connected to GND.
Input terminal of writing voltage to FUSE memory at 21 V.
(Refer to operation mode table.) Pull-down resistor built
in.
Clock input terminal of 6-bit counter. Operates at the
falling edge.
Reset input terminal of 6-bit counter. Operates at “L”.
Normally, connected to +1.1 to +5.5 V.
COUNTER Counter output terminal
OUT
V
SS
P
D
/V
PP
Negative power supply terminal
Program voltage input terminal
6
7
8
CLK
RST
V
DD
Clock input terminal
Reset input terminal
Positive power supply terminal
Mode Table
Table 2
Terminal
CE/PE
Read
P
D
/V
PP
V
SS
V
SS
V
PP
CLK
Input possible
Input impossible
Input impossible
RST
Input possible
Input impossible
Input impossible
DATA
Data output
High impedance
Data input
Read
Counter hold
Program
V
SS
V
DD
V
DD
Absolute Maximum Ratings
Table 3
Parameter
Power supply voltage
P
D
/V
PP
input voltage
Input voltage
Output voltage
Storage temperature
under bias
Storage temperature
Symbol
V
DD
V
PP
V
IN
V
OUT
V
bias
V
stg
Ratings
-0.3 to +6.5
-0.3 to 26
V
SS
-0.3 to V
DD
+0.3
V
SS
-0.3 to V
DD
+0.3
-30 to +85
-40 to +125
Unit
V
V
V
V
°C
°C
Recommended Operating Conditions
Table 4
Parameter
Power supply voltage
High level input voltage
Low level input voltage
Operating temperature
Symbol
V
DD
V
IH
V
IL
V
opr
Conditions
Ta=25°C, Read, t
CH
=15µs
Ta=25°C, Write
Ta=25°C, Read
Ta=25°C, Write
Ta=25°C, Read
Ta=25°C, Write
Min.
1.1
4.5
V
DD
-0.3
V
DD
-0.3
-0.3
-0.3
-20
Typ.
1.5
5.0
Max.
5.5
5.5
V
DD
V
DD
0.3
0.5
70
Unit
V
V
V
V
V
V
°C
2
Seiko Instruments Inc.
64-bit FUSE ROM
S-2100R
DC Electrical Characteristics
Table 5
Parameter
Operating current
consumption
Standby current
consumption
P
D
/V
PP
input voltage
P
D
/V
PP
input current
Output current
Pull-down resistance
Symbol
I
DDO
I
DDS
V
PP
I
PP
I
OH
I
OL
R
D
V
DD
=1.1 to 5.5 V, V
OH
=V
DD
-0.3 V
V
DD
=1.1 to 5.5 V, V
OH
=0.3 V
V
DD
=1.5 V
Conditions
V
DD
=1.5 V, f
CLK
=50 kHz
V
DD
=1.5 V, RST=V
DD
CLK=V
DD
, CE/PE=V
SS
Min.
20
-300
300
0.1
Typ.
21
0.2
Max.
20
0.3
22
150
0.4
Unit
µA
µA
V
mA
µA
µA
MΩ
AC Electrical Characteristics
1. Read mode
Table 6
(Ta=25°C, V
DD
=1.5 V)
Parameter
RST hold time
Read cycle time
CLK hold time
Access time
CE/PE setup time
RST setup time
CLK setup time
CE access time
Output disable time
CLK and RST inhibit time
Symbol
t
RH
t
RC
t
CH
t
ACC
t
CES
t
RS
t
CS
t
CE
t
WZ
t
CRI
Min.
5.0
2.0
5.0
2.0
5.0
5.0
Typ.
Max.
5.0
5.0
500
500
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
Load : 60 pF
2. Write mode
Parameter
CE-data setup time
Data setup time
Data hold time
CE-data hold time
V
PP
rise time
Program pulse width
V
PP
rise slope
Table 7
(Ta=25°C, V
DD
=5.0 V, V
PP
=21 V)
Symbol
t
CDS
t
DS
t
DH
t
CDH
t
r
t
PW
∆V
PP
Min.
0.5
0.5
0
2.0
20
8.0
Typ.
Max.
4
Unit
µs
µs
µs
µs
µs
ms
V/µs
Seiko Instruments Inc.
3
64-bit FUSE ROM
S-2100R
Read Mode Operation
By setting the CE/PE terminal to
“L”
level, the S-2100R enters the read mode. *
1
Next, adding an RST pulse causes the
contents of the memory bit of address 1 to be output at the DATA terminal; the rising of the RST pulse latches the data and
stabilizes it. *
2
Reading of addresses from 2 to 64 can be done by adding a CLK pulse sequentially after reading address 1. *
3
As soon as address 64 has been read, the COUNTER OUT terminal outputs
“H”
level. When it finishes reading address 64,
it does not accept any more CLK pulses and the counter does not operate. The data of address 64 is maintained till address
1 is read by the RST pulse.
CE/P
t
CES
t
RH
t
RC
t
CH
t
ACC
t
CE
t
ACC
Address 1 output
Address 2 output
Address 3 output
Address 1 output
RS
t
RC
t
RC
t
RS
CL
DATA
Figure 3 Read mode timing
*1
*2
*3
When both the CLK and RST terminals are at “H” level.
When the RST terminal is at
“L”
level, the latch is transparent and the data is recognized by the rising of the RST pulse.
Data read by the CLK pulse is latched at its rising.
Counter Hold Mode Operation
By setting the CE/PE terminal to
“H”
level, the S-2100R enters the counter hold mode and the DATA terminal becomes high
impedance. *
4
In counter hold mode, the CLK and RST pulses which fall while the CE/PE terminal is at “H” level are recognized to be invalid
and there is no change in counter and data output. When the CE/PE terminal is set to “L” level again, it returns to the
condition in which it was before the counter hold mode.
t
CES
CE/P
RST
t
CRI
t
CS
CLK
t
WZ
Address M
output
DATA
Address M+1 output
Address M+1 output
Figure 4 Counter hold mode timing
*
4
When both the CLK and RST terminals are at “H” level.
4
Seiko Instruments Inc.
stm32/stm8
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