DS04–21321–1aE
DATA SHEET
MB15A02
ASSP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
LOW POWER SERIAL INPUT PLL
SYNTHESIZER WITH 1.1GHZ PRESCALER
The Fujitsu MB15A02, utilizing Bi-CMOS technology, is a single chip serial input
PLL synthesizer with pulse-swallow function.
The MB15A02 contains a 1.1GHz two modulus prescaler that can select either a
64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit
latch, programmable reference divider (binary 14-bit programmable reference
counter), 1-bit switch counter, phase comparator with phase reverse function,
charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, and programmable
divider (binary 7-bit swallow counter and binary 11-bit programmable counter).
It operates supply voltage of 5V typ. and achieves very low supply current of 7mA
typ. realized through the use of Fujitsu Advanced Process Technology.
•
High operating frequency: f
IN MAX
=1.1GHz (P
IN MIN
=–10dBm)
PLASTIC PACKAGE
FPT-16P–M05
•
Pulse swallow function: 64/65 or 128/129
•
Low supply current: I
CC
=7mA typ.
•
Serial input 18-bit programmable divider consisting of:
– Binary 7-bit swallow counter: 0 to 127
– Binary 11-bit programmable counter: 16 to 2,047
•
Serial input 15-bit programmable reference divider consisting of:
– Binary 14-bit programmable reference counter: 6 to 16,383
– 1-bit switch counter (SW) sets divide ratio of prescaler
•
Two types of phase detector output
– On-chip charge pump (Bipolar type)
– Output for external charge pump
PLASTIC PACKAGE
FPT-16P–M06
•
Wide operating temperature: –40
°
C to +85
°
C
•
16–pin Plastic SOP Package
16–pin and 20–pin Plastic SSOP Packages
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Power Supply Voltage
Output Voltage
Open-drain Voltage
Output Current
Storage Temperature
Symbol
V
CC
V
P
V
OUT
V
OOP
I
OUT
T
STG
Rating
–0.5 to +7.0
V
CC
to 8.0
–0.5 to V
CC
+0.5
–0.5 to 6.0
Unit
V
V
V
V
mA
Remark
∅
P pin
PLASTIC PACKAGE
FPT-20P–M03
±
10
–55 to +125
°
C
NOTE:
Permanent device damage may occur if the above
Absolute Maximum
Ratings
are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. How-
ever, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated
voltages to this high impedance circuit.
Copyright
©
FUJITSU LIMITED and FUJITSUMICROELECTRONICS, INC.
1
MB15A02
PIN ASSIGNMENT
∅
R
NC
OSC
IN
OSC
IN
OSC
OUT
V
P
V
CC
D
O
GND
LD
fin
1
2
3
4
Top View
5
6
7
8
12 FC
11 LE
10 Data
9
Clock
NC
fin
(FPT–16P–M06)
(FPT–16P–M05)
D
O
GND
LD
16
∅
R
15
∅
P
14 f
OUT
13 NC
NC
OSC
OUT
V
P
V
CC
1
2
3
4
5
6
7
8
9
10
Top
View
20
19
18
17
16
15
14
13
12
11
∅
P
f
OUT
NC
FC
LE
Data
NC
Clock
(FPT–20P–M03)
2
MB15A02
BLOCK DIAGRAM
7
1
CRYSTAL
OSCILLATOR
OSC
OUT
2
MONITOR
FREQUENCY
CHANGING
CIRCUIT
fr
15
PHASE
COMPARATOR
16
LD
OSC
IN
∅
R
∅
P
PROGRAMMABLE REFERENCE
DIVIDER
BINARY 14-BIT
REFERENCE COUNTER
V
CC
4
14 f
OUT
GND
6
12 FC
15-BIT LATCH
15-BIT LATCH
CHARGE
PUMP
3
V
P
LE 11
19-BIT SHIFT REGISTER
Data 10
CONTROL
1-BIT
LATCH
19-BIT SHIFT REGISTER
5
D
O
Clock
9
18-BIT LATCH
7-BIT LATCH
11-BIT LATCH
f
IN
8
PRESCALER
PROGRAMMABLE DIVIDER
BINARY 7–BIT
SWALLOW
COUNTER
BINARY 11-BIT
PROGRAMMABLE
COUNTER
fp
CONTROL CIRCUIT
Note :
Pin numbers are based on SOP/SSOP 16–pin packages.
3
MB15A02
PIN DESCRIPTION
Pin No.
Pin Name
SOP–16P
SSOP–20P
SSOP–16P
1
2
3
4
5
6
7
8
9
1
3
4
5
6
7
8
10
11
OSC
IN
OSC
OUT
V
P
V
CC
D
O
GND
LD
f
IN
Clock
I/O
I
O
–
–
O
–
O
I
I
Description
Oscillator input.
Oscillator output.
A crystal is placed between OSC
IN
and OSC
OUT
.
Power supply pin for charge pump. When the internal charge pump is not
used, V
P
pin needs to be connected to V
CC
.
Power supply pin.
Charge pump output.
Ground.
Phase comparator output.
Normally this pin outputs high level. When there is a phase error between fr
and fp, LD becomes low for the period corresponding to the error.
Prescaler input.
The connection with an external VCO should be AC connection.
Clock input for 19-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into shift register.
Binary serial data input.
The last bit of data is a control bit. When this bit is high level, the data stored
in shift register is transferred to 15-bit latch. When this bit is low level and LE
is high level, the data is transferred to 18-bit latch.
Load enable input (with internal pull up resistor).
When LE is high, the data stored in shift register is transferred into latch ac-
cording to the control bit.
Phse select input of phase comparator (with internal pull up resistor).
When FC is low level, the characteristics of phase comparator is reversed.
FC input signal is also used to select fout pin (test pin) output, fr or fp.
No connection
Minitor pin of phase comparator input.
fout pin outputs either programmable reference divider output (fr) or pro-
grammable divider output (fp) according to FC pin input level.
FC=H: It is the same as fr output level.
FC=L: It is the same as fp output level.
Outputs for external charge pump.
The characteristics are reversed according to FC input.
∅
P pin is N-channel open drain output.
Outputs for external charge pump.
∅
R pin is CMOS output.
10
13
Data
I
11
14
LE
I
12
15
FC
I
13
2,9,12,16,19
NC
–
14
17
f
OUT
O
15
16
18
20
∅
P
∅
R
O
O
4
MB15A02
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift register and when load enable pin is high level or open, stored
data is transferred into latch according to the control bit.
Control data ”H” data is transferred into 15-bit latch.
Control data ”L” data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit programmable reference counter. Serial 16-bit
data format is shown below.
Direction of data shift
Control bit
Divide ratio of prescaler setting bit
LSB
MSB
C
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
W
Divide ratio of programmable reference counter setting bit
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
Ratio
R
6
7
S
14
0
0
S
13
0
0
S
12
0
0
S
11
0
0
S
10
0
0
S
9
0
0
S
8
0
0
S
7
0
0
S
6
0
0
S
5
0
0
S
4
0
0
S
3
1
1
S
2
1
1
S
1
0
1
•
16383
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
NOTES:
Divide ratio less than 6 is prohibited.
Divide ratio: 6 to 16,383
SW: This bit selects divide ratio of prescaler.
SW=H : 64/65
SW=L : 128/129
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets at high level).
Start data input with MSB first.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown following page.
5
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