September 1994
Edition 6.0
DATA SHEET
MB1501/MB1501H/MB1501L
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 1.1GHz PRESCALER
The Fujitsu MB1501/MB1501H/MB1501L, utilizing BI-CMOS technology, is a
single chip serial input PLL frequency synthesizer with pulse-swallow function.
The MB1501 series contain a 1.1GHz two modulus prescaler that can select either
64/65 or 128/129 divide ratio; control signal generator; 16-bit shift register; 15-bit
latch; programmable reference divider (binary 14-bit programmable reference
counter); 1-bit switch counter; phase comparator with phase inverse function;
charge pump; crystal oscillator; 19-bit shift register; 18-bit latch; programmable
divider (binary 7-bit swallow counter and binary 11-bit programmable counter).
The MB1501 operates on a low supply voltage (3V typ) and consumes low power
(45mW at 1.1GHz).
PLASTIC PACKAGE
DIP-16P-M04
MB1501 Product Line
D
O
Output
Width
MB1501 8V max 8.5V max Middle speed Middle
MB1501H 10V max 10.0V max High speed
Low
MB1501L 8V max 8.5V max Low speed
High
V
P
Voltage
V
OOP
Voltage
Lock up
time
High-level Low-level
Output
Output
Current
Current
Middle
Middle
High
Low
Low
High
•
•
•
•
•
High operating frequency: f
IN MAX
=1.1GHz (V
IN MIN
=0.20V
P-P
)
On-chip prescaler
Low power supply voltage: 2.7V to 5.5V (3.0V typ)
Low power supply consumption: 45mW (3.0V, 1.1GHz operation)
Serial input 18-bit programmable divider consisting of:
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
•
Serial input 15-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383)
1-bit switch counter (SW) Sets divide ratio of prescaler
•
2types of phase detector output
On-chip charge pump (Bipolar type)
Output for external charge pump
•
Wide operating temperature: T
A
=–40
°
C to +85
°
C
PLASTIC PACKAGE
FPT-16P-M06
PIN ASSIGNMENT
OSC
IN
1
OSC
OUT
2
V
P
3
V
CC
4
D
O
5
GND 6
( TOP VIEW )
16 ØR
15 ØP
14 f
P
13 f
r
12 FC
11 LE
10 Data
9 Clock
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Power Supply Voltage
Output Voltage
Open-drain Output
Output Current
Storage Temperature
NOTE:
Symbol
V
CC
V
PH
V
P
,V
PL
V
OUT
V
OOPH
V
OOP
,V
OOPL
Condition
MB1501H
MB1501/1501L
MB1501H
MB1501/1501L
Value
–0.5 to +7.0
V
CC
to 12.0
V
CC
to 10.0
–0.5 to V
CC
+0.5
–0.5 to 11.0
–0.5 to 9.0
±
10
–55 to +125
Unit
V
V
V
V
mA
°
C
LD 7
f
in
8
I
OUT
T
STG
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. How-
ever, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated volt-
ages to this high impedance circuit.
Permanent device damage may occur if the above
Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright
©
1994 by FUJITSU LIMITED
1
MB1501
MB1501H
MB1501L
MB1501/MB1501H/MB1501L BLOCK DIAGRAM
V
CC
4
16-Bit Shift Register
16-Bit Shift Register
GND
6
15-Bit Latch
13
12
7
Programmable
Reference Divider
f
r
FC
LD
OR
OP
LE
11
15-Bit Latch
OSC
IN
1
Crystal
Oscillator
Circuit
1-bit
Binary 14-Bit
Reference Counter SW
Phase
Comparator
16
15
OSC
OUT
2
19-Bit Shift Register
19-Bit Shift Register
3
Charge
Pump
5
f
in
8
Prescaler
Circuit
18-Bit Latch
7-Bit Latch
11-Bit Latch
14
f
P
D
O
V
P
Programmable Divider
Data
10
Control
1-Bit Latch
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Clock
9
Control Circuit
2
MB1501
MB1501H
MB1501L
PIN DESCRIPTIONS
Pin No.
1
2
Pin Name
OSC
IN
OSC
OUT
I/O
I
O
Descriptions
Oscillator input.
Oscillator output.
A crystal is placed between OSC
IN
and OSC
OUT
.
Power supply input for charge pump.
Power supply voltage input.
Charge pump output.
Phase characteristic can be inversed depending upon FC input.
Ground.
Phase comparator output.
This pin outputs high when the phase is locked. While the phase difference of f
r
and f
p
exists,
the output level goes low.
Prescaler input.
The connection with an external VCO should be an AC connection.
Clock input for 19-bit shift register and 16-bit shift register.
Each rising edge of the clock shifts one bit of data into the shift registers.
Serial data of binary code input.
The last bit of the data is a control bit. The last data bit specifies which latch is activated.
When the last bit is high level and LE is high-level, data is transferred to 15-bit latch.
When the last bit is low level and LE is high level, data is transferred to 18-bit latch.
Load enable input (with internal pull up resistor).
When LE is high level (or open), data stored in the shift register is transferred to latch depend-
ing on the control data.
Phase selecting input of phase comparator (with internal pull up resistor). When FC is low
level, charge pump and phase detector characteristics can be inversed.
Monitor pin of phase comparator input.
It is the same as programmable reference divider output.
Monitor pin of phase comparator input.
It is the same as programmable divider output.
Outputs for external charge pump.
Phase characteristics can be inversed depending on FC input.
OP
pin is an N-channel open-drain output.
3
4
5
6
V
P
V
CC
D
O
GND
—
—
O
—
7
LD
O
8
9
f
in
Clock
I
I
10
Data
I
11
LE
I
12
13
14
15
16
FC
f
r
f
P
OP
OR
O
O
O
O
O
3
MB1501
MB1501H
MB1501L
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using Data pin, Clock pin and LE pin, The 15-bit programmable reference divider and 18-bit programmable
divider are controlled respectively.
On rising edge of the clock shifts one bit of the data into the internal shift registers.
When load enable (LE) is high level (or open), data stored in shift resisters is transferred to 15-bit latch or 18-bit latch depending upon
the control bit level.
Control data “H” ; Data is transferred into 15-bit latch.
Control data “L” ; Data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.
Last data input
Control bit
LSB
S
1
S
2
S
3
S
4
S
5
S
6
Data input
Divide ratio of prescaler setting bit
MSB
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
First data input
C
SW
Divide ratio of programmable reference counter setting bits
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
ratio
R
8
9
S
14
0
0
S
13
0
0
S
12
0
0
S
11
0
0
S
10
0
0
S
9
0
0
S
8
0
0
S
7
0
0
S
6
0
0
S
5
0
0
S
4
1
1
S
3
0
0
S
2
0
0
S
1
0
1
•
16383
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
Divide ratio less than 8 is prohibited.
Divide ratio R: 8 to 16383
SW: Divide ratio of prescaler setting bit.
SW=“H” : 64
SW=“L” : 128
S
1
to S
14
: Divide ratio of programmable reference counter setting bits (8 to 16383)
C: Control bit (Control bit is set to high.)
4
MB1501
MB1501H
MB1501L
FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown below.
Last data input
Data input
Control bit
LSB
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
First data input
MSB
S
16
S
17
S
18
C
S
1
Divide ratio of swallow counter
setting bits
Divide ratio of programmable counter
setting bits
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide
ratio
A
0
1
S
7
0
0
S
6
0
0
S
5
0
0
S
4
0
0
S
3
0
0
S
2
0
0
S
1
0
1
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
ratio
N
16
17
S
18
0
0
S
17
0
0
S
16
0
0
S
15
0
0
S
14
0
0
S
13
0
0
S
12
1
1
S
11
0
0
S
10
0
0
S
9
0
0
S
8
0
1
•
127
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
2047
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
Divide ratio A : 0 to 127
Divide ratio less than 16 is prohibited.
Divide ratio N : 16 to 2047
S
8
to S
18
:Divide ratio of programmable counter setting bits (16 to 2047)
S
1
to S
7
: Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (Control bit is set to low.)
Dara is input from MSB data.
5
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