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FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers
September 2009
FIN1215 / FIN1216 / FIN1217/ FIN1218
LVDS 21-Bit Serializers / De-Serializers
Features
Low Power Consumption
20MHz to 85MHz Shift Clock Support
50% Duty Cycle on the Clock Output of Receiver
±1V Common-mode Range ~1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput: 1.785Gbps
Up to 595Mbps per Channel
Internal PLL with No External Components
Compatible with TIA/EIA-644 Specification
Offered in 48-lead TSSOP Packages
Description
The FIN1217 and FIN1215 transform 21-bit wide
parallel LVTTL (Low-Voltage TTL) data into three serial
LVDS (Low-Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data stream over a separate LVDS link.
Every cycle of transmit clock, 21 bits of input LVTTL
data are sampled and transmitted.
The FIN1216 and FIN1218 receives and converts the
three serial LVDS data streams back into 21 bits of
LVTTL data. Table 1 provides a matrix summary of the
serializers and de-serializers available. For the
FIN1217, at a transmit clock frequency of 85MHz, 21
bits of LVTTL data are transmitted at a rate of 595Mbps
per LVDS channel.
These chipsets solve EMI and cable size problems
associated with wide and high-speed TTL interfaces.
Ordering Information
Operating
Part Number Temperature
Range
FIN1215MTDX
FIN1216MTDX
FIN1217MTDX
FIN1218MTDX
(Preliminary)
For Fairchild’s definition of Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
Eco
Status
Package
Packing
Method
-40 to + 85°C
RoHS
48-Lead Thin Shrink Small Outline Package (TSSOP)
Tape and Reel
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers
Block Diagrams
Figure 1. FIN1217 / FIN1215 Transmitter Functional Diagram
Figure 2. FIN1218 / FIN1216 Receiver Functional Diagram
Table 1. Serializers / De-Serializers Chip Matrix
Part
FIN1215
FIN1216
FIN1217
FIN1218
CLK
Frequency
66
66
85
85
LVTTL IN
21
21
LVDS OUT
3
LVDS IN
LVTTL
OUT
21
21
Package
48-Lead TSSOP
3
3
3
48-Lead TSSOP
48-Lead TSSOP
48-Lead TSSOP
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
2
FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers
Transmitters
Pin Configuration
Figure 3. FIN1217 / FIN1215 (21:3 Transmitter)
Pin Definitions
Pin Names
TxIn
TxCKLIn
TxOut+
TxOut
TxCLKOut+
TxCLKOut-
/PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
NC
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
I/O
Type
I
I
O
O
O
O
I
I
I
I
I
I
I
# of
Pins
21
1
3
3
1
1
1
1
2
1
3
4
5
LVTTL Level Inputs
Description of Signals
LVTTL Level Clock Input; the rising edge is for data strobe
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
LVTTL Level Power-Down Input; assertion (LOW) puts the outputs in high-
impedance state
Power Supply Pin for LVDS Outputs
Ground Pins for PLL
Power Supply Pins for LVDS Outputs
Ground Pin for LVDS Outputs
Power Supply Pins for LVTTL Inputs
Ground Pins for LVTTL Inputs
No Connect
www.fairchildsemi.com
3
FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers
Receivers
Pin Configuration
Figure 4. FIN1216 / FIN1218 (3:21 Receiver)
Pin Definitions
Pin Names
RxIn
RxIn+
RxCLKIn-
RxCLKIn+
RxOut-
RxCLKOut
/PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
NC
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
I/O
Type
I
I
I
I
O
O
I
I
I
I
I
I
I
# of
Pins
3
3
1
1
21
1
1
1
2
1
3
4
5
Description of Signals
Negative LVDS Differential Data Output
Positive LVDS Differential Data Output
Negative LVDS Differential Clock Output
Positive LVDS Differential Clock Output
LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW
LVTTL Level Clock Output
LVTTL Level Input; Refer to Transmitter and Receiver Power-up and Power-down
Operation Truth Table
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pins for LVDS Inputs
Ground Pin for LVDS Inputs
Power Supply Pins for LVTTL Outputs
Ground Pins for LVTTL Outputs
No Connect
www.fairchildsemi.com
4
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