Philips Semiconductors
Product specification
SMPS control circuit
SG3524
DESCRIPTION
This monolithic integrated circuit contains all the control circuitry for
a regulating power supply inverter or switching regulator. Included in
a 16-pin dual-in-line package is the voltage reference, error
amplifier, oscillator, pulse-width modulator, pulse steering flip-flop,
dual alternating output switches and current-limiting and shut-down
circuitry. This device can be used for switching regulators of either
polarity, transformer-coupled DC-to-DC converters, transformerless
voltage doublers and polarity converters, as well as other power
control applications. The SG3524 is designed for commercial
applications of 0°C to +70°C.
PIN CONFIGURATION
D, F, N Packages
INVERT INPUT 1
NON-INV INPUT 2
OSC OUTPUT 3
(+)CL SENSE 4
(–)CL SENSE 5
R
T
6
C
T
7
16 V
REF
15 V
IN
14 EMITTER B
13 COLLECTOR B
12 COLLECTOR A
11 EMITTER A
10 SHUTDOWN
9
TOP VIEW
COMPENSATION
FEATURES
GROUND 8
•
Complete PWM power control circuitry
•
Single ended or push-pull outputs
•
Line and load regulation of 0.2%
•
1% maximum temperature variation
•
Total supply current is less than 10mA
•
Operation beyond 100kHz
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic Dual In-Line Package (DIP)
16-Pin Ceramic Dual In-Line Package (CERDIP)
16-Pin Small Outline (SO) Package
SL00174
Figure 1. Pin Configuration
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
0 to +70°C
ORDER CODE
SG3524N
SG3524F
SG3524D
DWG #
SOT38-4
0582B
SOT109-1
BLOCK DIAGRAM
V
REF
16
V
IN
15
REF
REG
+5V TO ALL
INTERNAL CIRCUITRY
+5V
OSCILLATOR
3
OUTPUT
FLIP FLOP
12
NOR
11
C
A
+5V
R
T
6
C
T
7
(RAMP)
OSC
+5V
+
COMPARATOR
–
+5V
ERROR
–
AMP
+
1k
10
SHUTDOWN
10k
9
COMPENSATION
+5V
+
CL
–
4
+SENSE
NOR
13
C
B
14 E
B
INV INPUT 1
N.I. INPUT 2
GROUND
8
(SUBSTRATE)
5 –SENSE
SL00175
Figure 2. Block Diagram
1994 Aug 31
1
853-0891 13721
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
IN
I
OUT
I
REF
P
D
Input voltage
Output current (each output)
Reference output current
Oscillator charging current
Power dissipation
Package limitation
Derate above 25°C
T
A
T
STG
Operating temperature range
Storage temperature range
1000
8
0 to +70
-65 to +150
mW
mW/°C
°C
°C
PARAMETER
RATING
40
100
50
5
UNIT
V
mA
mA
mA
DC ELECTRICAL CHARACTERISTICS
T
A
=0°C to +70°C, V
IN
=20V, and f=20kHz, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min
4.6
V
IN
=8 to 40V
I
L
=0 to 20mA
f=120Hz, T
A
=25°C
V
REF
=0, T
A
=25°C
Over operating temperature range
T
A
=25°C
C
T
=0.001
µF,
R
T
=2kΩ
R
T
and C
T
constant
V
IN
=8 to 40V, T
A
=25°C
Over operating temperature range
Pin 3, T
A
=25°C
C
T
=0.01
µF,
T
A
=25°C
V
CM
=2.5V
V
CM
=2.5V
68
T
A
=25°C
T
A
=25°C
A
V
=0dB, T
A
=25°C
T
A
=25°C
% each output “ON”
Zero duty cycle
Maximum duty cycle
0.5
0
1
3.5
1
Pin 9=2V with error amplifier set for maximum out,
T
A
=25°C
180
200
0.2
-1
+1
220
1.8
70
3
3.8
45
3.5
0.5
2
2
80
3.4
10
10
Typ
5.0
10
20
66
100
0.3
20
300
5
1
2
1
Max
5.4
30
50
UNIT
Reference section
V
OUT
Output voltage
Line regulation
Load regulation
Ripple rejection
I
SC
Short circuit current limit
Temperature stability
Long-term stability
V
mV
mV
dB
mA
%
mV/kHz
kHz
%
%
%
V
P
µs
mV
µA
dB
V
dB
MHz
V
%
V
V
µA
mV
mV/°C
V
Oscillator section
f
MAX
Maximum frequency
Initial accuracy
Voltage stability
Temperature stability
Output amplitude
Output pulse width
Error amplifier section
V
OS
I
BIAS
V
CM
CMRR
BW
V
OUT
Input offset voltage
Input bias current
Open-loop voltage gain
Common-mode voltage
Common-mode rejection ratio
Small-signal bandwidth
Output voltage
Duty cycle
Input threshold
Input threshold
I
BIAS
Input bias current
Sense voltage
Sense voltage T.C.
V
CM
Common-mode voltage
Comparator section
Current limiting section
1994 Aug 31
2
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
DC ELECTRICAL CHARACTERISTICS
(Continued)
T
A
= 0°C to +70°C, V
IN
= 20V, and f = 20kHz, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min
40
V
CE
=40V
I
C
=50mA
V
IN
=20V
R
C
=2kΩ, T
A
=25°C
R
C
=2kΩ, T
A
=25°C
17
0.1
1
18
0.2
0.1
50
2
Typ
Max
UNIT
Output section
(each output)
Collector-emitter voltage (breakdown)
Collector-leakage current
Saturation voltage
Emitter output voltage
t
R
t
F
Rise time
Fall time
(excluding oscillator charging current,
error and current limit dividers, and
with outputs open)
V
µA
V
V
µs
µs
Total standby current
V
IN
=40V
8
10
mA
THEORY OF OPERATION
Voltage Reference
An internal series regulator provides a nominal 5V output which is
used both to generate a reference voltage and is the regulated
source for all the internal timing and controlling circuitry. This
regulator may be bypassed for operation from a fixed 5V supply by
connecting Pins 15 and 16 together to the input voltage. In this
configuration, the maximum input voltage is 6.0V.
This reference regulator may be used as a 5V source for other
circuitry. It will provide up to 50mA of current itself and can easily be
expanded to higher currents with an external PNP as shown in
Figure 3.
Q1
100Ω
+V
IN
15
SG3524
REFERENCE
SECTION
8
16
+
10µF
V
REF
I
L
to 1.0A
DEPENDING
ON CHOICE
FOR Q1
GND
SL00176
Figure 3. Expanded Reference Current Capability
TEST CIRCUIT
I
S
OSC OUT
V
REF
2k
1W
15
3
16
8
6
7
RAMP
V
IN
8–40V
2k
2
N.I.
INPUT
1
INV.
INPUT
9
COMP
SHUT
DOWN
10k
10
4
SG3524
12
13
11
5 14
CURRENT
LIMIT
2k
1W
OUTPUTS
V
IN
0.1
R
T
C
T
10k
2k
1k
SL00177
Figure 4. Test Circuit
1994 Aug 31
3
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
3.6 V
÷
R
T
and should be kept within the approximate range of 30µA
to 2mA; i.e., 1.8k<R
T
<100k.
OUTPUT DEAD TIME – microseconds
10
5
3
2
1.0
0.5
0.3
.001 .002 .005 .01 .02
.05 1
TIMING CAPACITOR VALUE (C–)–(µF)
SL00178
Figure 5. Output Stage Dead Time as a Function of the Timing
Capacitor Value
The range of values for C
T
also has limits as the discharge time of
C
T
determines the pulse-width of the oscillator output pulse. This
pulse is used (among other things) as a blanking pulse to both
outputs to insure that there is no possibility of having both outputs
on simultaneously during transitions. This output dead time
relationship is shown in Figure 5. A pulse width below approximately
0.5µs may allow false triggering of one output by removing the
blanking pulse prior to the flip-flop’s reaching a stable state. If small
values of C
T
must be used, the pulse-width may still be expanded
by adding a shunt capacitance (≅100pF) to ground at the oscillator
output. [(Note: Although the oscillator output is a convenient
oscilloscope sync input, the cable and input capacitance may
increase the blanking pulse-width slightly.)] Obviously, the upper
limit to the pulse width is determined by the maximum duty cycle
acceptable. Practical values of C
T
fall between 0.001 and 0.1
µF.
The oscillator period is approximately t=R
T
C
T
where t is in
microseconds when R
T
=Ω and C
T
=µF. The use of Figure 6 will allow
selection of R
T
and C
T
for a wide range of operating frequencies.
Note that for series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle and the
frequency of the oscillator is the frequency of the output. For
push-pull applications, the outputs are separated and the flip-flop
divides the frequency such that each output’s duty cycle is 0-45%
and the overall frequency is one-half that of the oscillator.
TIMING RESISTOR (R T ) kohms
100
50
20
10
5
2
1
5 10 20 50 100 200 5001ms2ms
OSCILLATOR PERIOD (µs)
External Synchronization
If it is desired to synchronize the SG3524 to an external clock, a
pulse of
≅+3V
may be applied to the oscillator output terminal with
R
T
C
T
set slightly greater than the clock period. The same
considerations of pulse-width apply. The impedance to ground at
this point is approximately 2kΩ.
If two or more SG3524s must be synchronized together, one must
be designated as master with its R
T
C
T
set for the correct period.
The slaves should each have an R
T
C
T
set for approximately 10%
longer period than the master with the added requirement that
C
T
(slave)=one-half C
T
(master). Then connecting Pin 3 on all units
together will insure that the master output pulse—which occurs first
and has a wider pulse width—will reset the slave units.
SL00179
Figure 6. Oscillator Period
as a Function of R
T
and C
T
R
L
= 30MΩ
VOLTAGE GAIN - dB
80
60
40
20
0
10
R
L
= RESISTANCE FROM
PIN 9 TO GND
100
1k
10k
100k 1M
FREQUENCY - (Hz)
10M
R
L
= 1MΩ
R
L
= 300kΩ
R
L
= 100kΩ
R
L
= 30kΩ
Error Amplifier
This circuit is a simple differential input transconductance amplifier.
The output is the compensation terminal, Pin 9, which is a
high-impedance node (R
L
≅
5MΩ). The gain is
A
V
+
g
M
R
L
+
8 I
C
R
L
2kT
[
0.002R
L
and can easily be reduced from a nominal of 10,000 by an external
shunt resistance from Pin 9 to ground, as shown in Figure 7.
SL00180
Figure 7. Amplifiers Open-Loop Gain as a Function of
Frequency and Loading on Pin 9
In addition to DC gain control, the compensation terminal is also the
place for AC phase compensation. The frequency response curves
of Figure 7 show the uncompensated amplifier with a single pole at
approximately 200Hz and a unity gain crossover at 5MHz.
Typically, most output filter designs will introduce one or more
additional poles at a significantly lower frequency. Therefore, the
best stabilizing network is a series RC combination between Pin 9
and ground which introduces a zero to cancel one of the output filter
poles. A good starting point is 50kΩ plus 0.001µF.
Oscillator
The oscillator in the SG3524 uses an external resistor (R
T
) to
establish a constant charging current into an external capacitor (C
T
).
While this uses more current than a series-connected RC, it
provides a linear ramp voltage on the capacitor which is also used
as a reference for the comparator. The charging current is equal to
1994 Aug 31
4
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
One final point on the compensation terminal is that this is also a
convenient place to insert any programming signal which is to
override the error amplifier. Internal shutdown and current limit
circuits are connected here, but any other circuit which can sink
200µA can pull this point to ground, thus shutting off both outputs.
While feedback is normally applied around the entire regulator, the
error amplifier can be used with conventional operational amplifier
feedback and is stable in either the inverting or non-inverting mode.
Regardless of the connections, however, input common-mode limits
must be observed or output signal inversions may result. For
conventional regulator applications, the 5V reference voltage must
be divided down as shown in Figure 8. The error amplifier may also
be used in fixed duty cycle applications by using the unity gain
configuration shown in the open-loop test circuit.
V
REF
5k
R
2
POSITIVE
OUTPUT
VOLTAGES
2
1
+
–
5k
GND
R
1
V
REF
R
1
5k
2
1
5k
GND
R
2
+
–
NEGATIVE
OUTPUT
VOLTAGES
Current Limiting
The current limiting circuitry of the SG3524 is shown in Figure 9.
By matching the base-emitter voltages of Q1 and Q2, and assuming
a negligible voltage drop across R
1
:
Threshold=V
BE
(Q1)+I
1
R
2
-V
BE
(Q2)
=I
1
R
2
≅
200mV
Although this circuit provides a relatively small threshold with a
negligible temperature coefficient, there are some limitations to its
use, the most important of which is the
±1V
common-mode range
which requires sensing in the ground line. Another factor to consider
is that the frequency compensation provided by R
1
C
1
and Q1
provides a roll-off pole at approximately 300Hz.
Since the gain of this circuit is relatively low, there is a transition
region as the current limit amplifier takes over pulse width control
from the error amplifier. For testing purposes, threshold is defined as
the input voltage required to get 25% duty cycle with the error
amplifier signaling maximum duty cycle.
In addition to constant current limiting, Pins 4 and 5 may also be
used in transformer-coupled circuits to sense primary current and to
shorten an output pulse, should transformer saturation occur.
Another application is to ground Pin 5 and use Pin 4 as an additional
shutdown terminal: i.e., the output will be off with Pin 4 open and on
when it is grounded. Finally, foldback current limiting can be
provided with the network of Figure 10. This circuit can reduce the
short-circuit current (I
SC
) to approximately one-third the maximum
available output current (I
MAX
).
9
SL00181
Figure 8. Error Amplifier Biasing Circuits
RAMP
t
1
R
1
ERROR
AMPLIFIER
C
1
R
1
Q1
Q2
COMPARATOR
5
–
SENSE
+
4
SL00182
Figure 9. Current Limiting Circuitry of the SG3524
V
O
= 5V
S
A
/S
B
R
1
R
2
R
S
–
SENSE
+
5
4
I MAX
+
+
1
R
S
V
)
V 0R 2
R1
)
R2
TH
I
V TH
R
S
where
SC
NOTE:
V
TH
= 200mV
Foldback current limiting can be used to reduce power dissipation
under shorted output conditions.
SL00183
Figure 10. Foldback Current Limiting
1994 Aug 31
5
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