FUJITSU SEMICONDUCTOR
DATA SHEET
DS706-00011-0v01-E
32-bit ARM
TM
Cortex
TM
-M3 based Microcontroller
FM3 MB9A110 Series
MB9AF112L/M/N, F114L/M/N, F115M/N, F116M/N
DESCRIPTION
The MB9A110 Series are a highly integrated 32-bit microcontroller that target for high-performance and
cost-sensitive embedded control applications.
The MB9A110 Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM,
and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (UART,
SIO, I
2
C, LIN).
The products which are described in this data sheet are placed into TYPE1 product categories in "FM3
FAMILY MB9Axxx/MB9Bxxx SERIES PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Copyright
2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.4
MB9A110 Series
FEATURES
32-bit ARM Cortex-M3 Core
・
Processor version: r2p1
・
Up to 40MHz Frequency Operation
・
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
・
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
・
Up to 512 Kbyte
・
Read cycle: 0wait-cycle
・
Security function for code protection
[SRAM]
This Series contain a total of up to 32Kbyte on-chip SRAM memories. This is composed of two
independent SRAM for CPU and DMA Controller can process simultaneously.
・
Up to 16 Kbyte SRAM for high-performance CPU
・
Up to 16 Kbyte SRAM for CPU/DMA Controller
External Bus Interface*
・
Supports SRAM, NOR Flash device
・
Up to 8 chip selects
・
8/16-bit Data width
・
Up to 25-bit Address bit
・
Suports Address/Data multiplex
* : MB9AF112L, F114L do not support External Bus Interface
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DS706-00011-0v01-E
MB9A110 Series
Multi-function Serial Interface (Max. 8channels)
・
4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
・
Operation mode is selectable from the followings for each channel.
・
UART
・
CSIO
・
LIN
・
I
2
C
[UART]
・
Full-duplex double buffer
・
Selection with or without parity supported
・
Built-in dedicated baud rate generator
・
External clock available as a serial clock
・
Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*
・
Various error detect functions available (parity errors, framing errors, and overrun errors)
* : MB9AF112L, F114L do not support Hardware Flow control
[CSIO]
・
Full-duplex double buffer
・
Built-in dedicated baud rate generator
・
Overrun error detect function available
[LIN]
・
LIN protocol Rev.2.1 supported
・
Full-duplex double buffer
・
Master/Slave mode supported
・
LIN break field generate (can be changed 13-16bit length)
・
LIN break delimiter generate (can be changed 1-4bit length)
・
Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
・
Standard mode (Max.100kbps) / High-speed mode (Max.400Kbps) supported
DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・
8 independently configured and operated channels
・
Transfer can be started by software or request from the built-in peripherals
・
Transfer address area: 32bit(4Gbyte)
・
Transfer mode: Block transfer/Burst transfer/Demand transfer
・
Transfer data type: byte/half-word/word
・
Transfer block count: 1 to 16
・
Number of transfers: 1 to 65536
A/D Converter (Max. 16channels)
[12-bit A/D Converter]
・
Successive Approximation Register type
・
Built-in 3unit*
・
Conversion time: 1.0μs@5V
・
Priority conversion available (priority at 2levels)
・
Scanning conversion mode
・
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
* : MB9AF112L, F114L built-in 2unit
DS706-00011-0v01-E
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MB9A110 Series
Base Timer (Max. 8channels)
Operation mode is selectable from the followings for each channel.
・
16-bit PWM timer
・
16-bit PPG timer
・
16/32-bit reload timer
・
16/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as I/O ports when they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.
・
Capable of pull-up control per pin
・
Capable of reading pin level directly
・
Built-in the port relocate function
・
Up to 83 fast I/O Ports@100pin Package
・
Some pins are 5V tolerant I/O (MB9AF115M/N, MB9AF116M/N only)
Please see "PIN DESCRIPTION" to confirm the corresponding pins.
Multi-function Timer (Max. 2unit)
The Multi-function timer is composed of the following blocks.
・
16-bit free-run timer × 3ch/unit
・
Input capture × 4ch/unit
・
Output compare × 6ch/unit
・
A/D activating compare × 3ch/unit
・
Waveform generator × 3ch/unit
・
16-bit PPG timer × 3ch/unit
The following function can be used to achieve the motor control.
・
PWM signal output function
・
DC chopper waveform output function
・
Dead time function
・
Input capture function
・
A/D convertor activate function
・
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC) (Max. 2unit)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・
16-bit position counter
・
16-bit revolution counter
・
Two 16-bit compare registers
Dual Timer (Two 32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・
Free-running
・
Periodic (=Reload)
・
One-shot
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DS706-00011-0v01-E
MB9A110 Series
Watch Counter
The Watch counter is used for wake up from power saving mode.
・
Interval timer: up to 64s(Max.)@ Sub Clock : 32.768kHz
External Interrupt Controller Unit
・
Up to 16 external vectors
・
Include one non-maskable interrupt(NMI)
Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed CR oscillator. Therefore,”Hardware" watchdog is
active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・
CCITT CRC16 Generator Polynomial: 0x1021
・
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and PLL) that are dynamically selectable.
・
Main Clock
・
Sub Clock
・
High-speed CR Clock
・
Low-speed CR Clock
・
PLL Clock
: 4 to 48MHz
: 32.768kHz
: 4MHz
: 100kHz
[Resets]
Reset requests from INITX pins, Power on reset, Software reset, watchdog timers reset, low voltage
detector reset and clock supervisor reset.
Clock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.
・
External OSC clock failure (clock stop) is detected, reset is asserted.
・
External OSC frequency anomaly is detected, interrupt or reset is asserted.
Low Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has
been set, Low Voltage Detector generates an interrupt or reset.
・
LVD1: error reporting via interrupt
・
LVD2: auto-reset operation
DS706-00011-0v01-E
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