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LH543620M-30: 产品描述FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144; 产品类别存储存储; 文件大小278KB，共40页; 制造商SHARP; 官网地址http://sharp-world.com/products/device/

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LH543620M-30概述

FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144

LH543620M-30规格参数

参数名称	属性值
是否Rohs认证	不符合
包装说明	20 X 20 MM, PLASTIC, TQFP-144
Reach Compliance Code	unknown
Is Samacsys	N
其他特性	RETRANSMIT
周期时间	30 ns
JESD-30 代码	S-PQFP-G144
JESD-609代码	e0
长度	20 mm
内存密度	36864 bit
内存宽度	36
功能数量	1
端子数量	144
字数	1024 words
字数代码	1000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	1KX36
输出特性	3-STATE
可输出	YES
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行	PARALLEL
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
宽度	20 mm
Base Number Matches	1

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LH543620

FEATURES

•

Fast Cycle Times: 20/25/30 ns

•

Selectable 36/18/9-Bit Word Width for Both

Input Port and Output Port

•

Byte-Order-Reversal Function (i.e.,

‘Big-Endian’

‘Little-Endian’ Conversion)

•

16-mA-I

Three-State Outputs

•

Automatic Byte Parity Checking

•

Selectable Byte Parity Generation

•

Five Status Flags: Full, Almost-Full,

Half-Full, Almost-Empty, and Empty

•

All FIFO Status Flags are Synchronous

(AE, HF, AF Through Programming of

Control Register)

•

Programmed Values may be entered from

either Port

•

Two Enable Control Signals for each Port

•

Mailbox Register with Synchronized Flags

•

Asynchronous Data-Bypass Function

•

‘Smart’ Data-Retransmit Function

•

Configurable for Paralleled FIFO Operation

(72-Bit Data Width)

•

Space-Saving PQFP and TQFP

Packages

•

PQFP-to-PGA Package Conversion

1024

36 Synchronous FIFO

FUNCTIONAL DESCRIPTION

The LH543620 is a FIFO (First-In, First-Out) memory

device, based on fully-static CMOS RAM technology,

capable of containing up to 1024 36-bit words. It can

replace four or more nine-bit-wide FIFOs in many appli-

cations.

The input port and the output port operate inde-

pendently of each other. Write operations are performed

on the rising edge of the input clock CKI, and enabled by

two enabled signals ENI

, ENI

. Read operations are

performed on the rising edge of the output clock CKO and

enabled by two enabled signals ENO

, ENO

Five status flags are available to monitor the memory

array status: Full, Almost-Full, Half-Full, Almost-Empty,

and Empty. The Almost-Full and Almost-Empty flags are

initialized to a default offset of eight locations from their

respective boundaries, but they are each programmable

over the entire FIFO depth.

Both the input port and the output port may be set

independently to operate at three data-word widths: 36

bits, 18 bits, or 9 bits. This setting may be changed during

system operation. The LH543620 can perform Byte-Or-

der-Reversal on the four nine-bit bytes of each 36-bit data

word passing through it, thus accomplishing ‘Big Endian’

↔

‘Little Endian’ conversion.

When data is read out of the FIFO a byte-parity check

is performed. The parity flag is used to indicate that a

parity error was detected in one of the 9-bit bytes of the

output word.

Parity generation, when selected, creates the parity bit

of each 8-bit byte of the input word. The result is written

into the MSB-bit of each 9-bit byte, overwriting the pre-

vious contents of the bit. The default is odd parity. How-

ever, the FIFO may be programmed to use even parity.

The LH543620 has a data-bypass mode that connects

the output port to the input port asynchronously. A mailbox

facility with Synchronized Flags is provided from the input

port to the output port.

The LH543620’s ‘Smart-Retransmit’ capability sets the

internal-memory read pointer to any arbitrary memory

location. The ‘Smart-Retransmit’ capability includes a

Marking Function and a Programmable Offset to support

data communication and digital signal processing appli-

cations.

NOTES:

1. This is a final data sheet; except that all references to the TQFP

package have Preliminary status.

2. For PQFP-to-PGA conversion for thru-hole board designs,

SHARP recommends ITT Pomona Electronics’ SMT/PGA Ge-

neric Converter model #5853

. This converter maps the

LH543620 132-pin PQFP to a generic 13

13, 132-pin PGA

(100-mil pitch). For more information, contact SHARP or ITT Po-

mona Electronics at 1500 East Ninth Street, Pomona, CA

2-410

LH543620M-30相似产品对比

	LH543620M-30	LH543620M-25	LH543620P-25	LH543620M-20	LH543620P-20	LH543620P-30
描述	FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144	FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144	FIFO, 1KX36, Synchronous, CMOS, PQFP132, 0.950 X 0.950 INCH, PLASTIC, QFP-132	FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144	FIFO, 1KX36, Synchronous, CMOS, PQFP132, 0.950 X 0.950 INCH, PLASTIC, QFP-132	FIFO, 1KX36, Synchronous, CMOS, PQFP132, 0.950 X 0.950 INCH, PLASTIC, QFP-132
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
包装说明	20 X 20 MM, PLASTIC, TQFP-144	20 X 20 MM, PLASTIC, TQFP-144	BQFP,	20 X 20 MM, PLASTIC, TQFP-144	BQFP,	BQFP,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
其他特性	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT
周期时间	30 ns	25 ns	25 ns	20 ns	20 ns	30 ns
JESD-30 代码	S-PQFP-G144	S-PQFP-G144	S-PQFP-G132	S-PQFP-G144	S-PQFP-G132	S-PQFP-G132
JESD-609代码	e0	e0	e0	e0	e0	e0
长度	20 mm	20 mm	24.13 mm	20 mm	24.13 mm	24.13 mm
内存密度	36864 bit	36864 bit	36864 bit	36864 bit	36864 bit	36864 bit
内存宽度	36	36	36	36	36	36
功能数量	1	1	1	1	1	1
端子数量	144	144	132	144	132	132
字数	1024 words	1024 words	1024 words	1024 words	1024 words	1024 words
字数代码	1000	1000	1000	1000	1000	1000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	1KX36	1KX36	1KX36	1KX36	1KX36	1KX36
输出特性	3-STATE	3-STATE	TOTEM POLE	3-STATE	TOTEM POLE	TOTEM POLE
可输出	YES	YES	YES	YES	YES	YES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP	BQFP	LFQFP	BQFP	BQFP
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, BUMPER	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, BUMPER	FLATPACK, BUMPER
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	4.57 mm	1.6 mm	4.57 mm	4.57 mm
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.635 mm	0.5 mm	0.635 mm	0.635 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
宽度	20 mm	20 mm	24.13 mm	20 mm	24.13 mm	24.13 mm
Is Samacsys	N	N	N	N	N	-
Base Number Matches	1	1	1	1	1	-

LH543620M-30

LH543620M-30概述

LH543620M-30规格参数

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LH543620M-30相似产品对比

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