32K x 32 EEPROM MODULE
EEPROM
PUMA 2E1000-70/90/12
Issue 4.4 : January 2001
Description
The PUMA 2E1000 is a 1Mbit High Speed
EEPROM module user configurable as
32Kx32, 64Kx16 or 128Kx8.
Available with access times of 70, 90 &
120ns the device has an industry standard
ceramic 66 pin P.G.A footprint.
The device features byte and page write
facility, 10,000 Write Erase cycle capability
and data retention time of 10 years.
The device may be screened in accordance
with MIL-STD-883
1,048,576 bit CMOS High Speed EEPROM
Features
Very Fast access times of 70/90/120 ns.
User Configurable as 8 / 16 / 32 bit wide.
Upgradeable footprint.
Operating Power
1760 mW (max).
Standby Power
1320 mW (max).
Package Suitable for Thermal Ladder Applications.
Single byte and Page Write operation.
DATA Polling and Toggle Bit for End of Write Detection.
Hardware and Software Data Protection.
May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definition
12
23
34
45
56
1
D8
2
WE2
13
D15
24
D24
35
VCC
46
D31
57
D9
CS2
14
D14
25
D25
36
CS4
47
D30
58
A0~A14
OE
WE4
WE3
WE2
WE1
3
D10
4
GND
15
D13
26
D26
37
WE4
48
D29
59
A13
5
D11
16
D12
27
A6
D27
49
D28
60
32K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
32K x 8
EEPROM
32K x 8
EEPROM
32K x 8
EEPROM
A14
6
A10
17
OE
28
NC
7
A11
18
NC
29
VIEW
FROM
ABOVE
38
A7
39
A3
50
A0
61
NC
40
A4
51
A1
62
NC
8
A12
19
WE1
30
A8
41
A5
52
A2
63
NC
9
VCC
20
D7
31
A9
42
WE3
53
D23
64
D0
10
CS1
21
D6
32
D16
43
CS3
54
D22
65
D1
11
NC
22
D5
33
D17
44
GND
55
D21
66
D2
D3
D4
D18
D19
D20
Pin Functions
A0-14
CS1-4
WE1-4
V
CC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0-31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Temperature Under Bias
Storage Temperature
All input voltages (including N.C. pins) with Respect to GND
All output voltages with respect to GND
Voltage on OE and A9 with Respect to GND
T
BIAS
T
STG
V
T
V
OUT
V
OEA
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to V
CC
+0.6
-0.6 to +13.5
°C
°C
V
V
V
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated below is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
Symbol
V
CC
V
IL
V
IH
T
A
T
AI
T
AM
min
4.5
-0.1
2.0
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
0.8
V
CC
+1
70
85
125
V
V
V
°
C
°
C (2E1000I)
°
C (2E1000M, MB)
DC Electrical Characteristics
(V
CC
=5.0V±10%, T
A
=-55 to +125°C)
Parameter
Input Leakage Current
Address, OE
CS1~4, WE1~4
Output Leakage Current
Operating Supply Current
Standby Supply Current
Output Low Voltage
Output High Voltage
Symbol Test Condition
I
LI1
I
LI2
I
LO
I
CC32
I
SB1
V
OL
V
OH
0V
≤
V
IN
≤
V
CC
+1V
As above.
CS1~4=V
IH
, V
I/O
=GND to VCC
f=5MHz, I
I/O
=0mA
2.0V
≤
CS1~4
≤
V
CC
+1V
min
-
-
-
-
-
-
2.4
typ
-
-
-
-
-
-
-
max
40
10
40
320
240
0.45
-
Unit
µA
µA
µA
mA
mA
V
V
I
OL
= 6.0mA
I
OH
= -4.0mA
Capacitance
(V
CC
=5V±10%,T
A
=25
°
C)
Parameter
Input Capacitance:
I/O Capacitance:
Symbol
C
IN
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V, 8 bit mode
typ
26
42
max
34
58
Unit
pF
pF
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* V
CC
=5V±10%
Output Test Load
I/O Pin
645
Ω
1.76V
100pF
2
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
AC READ CHARACTERISTICS
Read Cycle
Parameter
Read Cycle Time
Address to Output Delay
CS1~4 to Output Delay
(1)
OE to Output Delay
(2)
CS1~4 or OE to Output Float
(3,4)
Output Hold from OE, CS1~4 or
Address, (whichever occured first)
Symbol
t
RC
t
ACC
t
CS
t
OE
t
DF
t
OH
-70
min max
-
-
-
0
0
0
70
70
70
40
40
-
-90
min max
-
-
-
0
0
0
90
90
90
45
45
-
-12
min max
-
-
-
0
0
0
120
120
120
50
50
-
Unit
ns
ns
ns
ns
ns
ns
Notes: (1) CS1~4 may be delayed up to t
ACC
- t
CS
after the address transition without impact on t
ACC
.
(2) OE may be delayed up to t
CS
- t
OE
after the falling edge of CS1~4 without impact on t
CS
or by t
ACC
- t
OE
after an
address change without impact on t
ACC
.
(3) t
DF
is specified from OE or CS1~4 whichever occurs first (C
L
= 5pF).
(4) This parameter is only sampled and is not 100% tested.
Write Cycle
Parameter
Address, OE Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width
(WE1~4 or CS1~4)
Data Set-up Time
Data, OE Hold Time
Time to Data Valid
Note: (1) NR = No Restriction
Page Mode Write Cycle
Symbol
t
AS
, t
OES
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH
, t
OEH
t
DV
min
0
50
0
0
100
50
0
NR
(1)
typ
-
-
-
-
-
-
-
-
max
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte/Word Load Cycle Time
Write Pulse Width High
Symbol
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
min
-
0
50
50
0
100
-
50
typ
5
-
-
-
-
-
-
-
max
10
-
-
-
-
-
150
-
Unit
ms
ns
ns
ns
ns
ns
µs
ns
See notes on page 6, Mode Write Waveform.
DATA Polling Characteristics
Parameter
Data Hold Time
OE Hold Time
OE to Output Delay
(1)
Write Recovery Time
Symbol
t
DH
t
OEH
t
OE
t
WR
min
0
0
0
typ
-
-
-
max
-
-
-
Unit
ns
ns
ns
ns
Note : (1) See AC Read Characteristics.
3
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
Toggle Bit Characteristics
(1,2,3,4)
Parameter
Data Hold Time
OE Hold Time
OE to Output Delay
(1)
OE High Pulse
Write Recovery Time
Symbol
t
DH
t
OEH
t
OE
t
OEHP
t
WR
min
10
10
150
0
typ
-
-
-
-
max
-
-
-
-
Unit
ns
ns
ns
ns
ns
Note : (1) See AC Read Characteristics.
(2) Toggling either OE or CS1~4, or both OE and CS1~4 will operate toggle bit.
(3) Beginning and ending state of D6 will vary.
(4) Any address location may be used but the address should not vary.
Read Cycle Timing Waveform
(1,2,3,4)
Address
Address Valid
t
RC
CS1~4
t
CS
t
OE
OE
t
DF
t
ACC
t
OH
Output
Valid
DATA OUT
HIGH Z
AC Write Waveform - WE1~4 Controlled
t
WC
Address
t
AS
WE1~4
t
AH
t
WPH
t
WP
t
CS
t
CH
CS1~4
t
OES
O
E
t
DV
DATA IN
High-Z
t
OEH
Data Valid
High-Z
t
DS
t
DH
4
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
AC Write Waveform - CS1~4 Controlled
t
WC
Address
t
AS
t
CS
WE1~4
t
AH
t
CH
t
WP
CS1~4
t
OES
OE
t
WPH
t
OEH
t
DV
DATA IN
High-Z
Data Valid
t
DS
t
DH
High-Z
Page Mode Write Waveform
(1,2)
OE
CS1~4
t
WP
t
WPH
t
BLC
WE1~4
t
AS
t
AH
Valid
Add
t
DH
A0-A5
t
DS
Data
Valid
Data
Byte 0
Byte 1
Byte 2
Byte 3
Byte 62
Byte 63
t
WC
Note: (1) A6 through A14 must specify the page address during each high to low transition of WE1~4 (or CS1~4).
(2) OE must be high only when WE1~4 and CS1~4 are both low.
5
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