www.ti.com
SN74ALVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES125J – FEBRUARY 1998 – REVISED NOVEMBER 2004
FEATURES
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max t
pd
of 2 ns at 3.3 V
±24-mA
Output Drive at 3.3 V
Ideal for Use in PC100 Register DIMM,
Revision 1.1
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus driver is designed for 1.65-V
to 3.6-V V
CC
operation.
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
high. The A data is latched if the clock (CLK) input is
held at a high or low logic level. If LE is low, the A
data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is high, the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
NC − No internal connection
ORDERING INFORMATION
T
A
SSOP - DL
-40°C to 85°C
TSSOP - DGG
TVSOP - DGV
VFBGA - GQL
VFBGA - ZQL (Pb-free)
PACKAGE
(1)
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
ORDERABLE PART NUMBER
SN74ALVC16835DL
SN74ALVC16835DLR
SN74ALVC16835DGGR
SN74ALVC16835DGVR
SN74ALVC16835GQLR
SN74ALVC16835ZQLR
TOP-SIDE MARKING
ALVC16835
ALVC16835
VC835
VC835
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2004, Texas Instruments Incorporated
SN74ALVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES125J – FEBRUARY 1998 – REVISED NOVEMBER 2004
www.ti.com
GQL OR ZQL PACKAGE
(TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
2
3
4
5
6
TERMINAL ASSIGNMENTS
(1)
1
A
B
C
D
E
F
G
H
J
K
(1)
Y1
Y3
Y5
Y7
Y9
Y10
Y12
Y14
Y16
Y18
2
NC
Y2
Y4
Y6
Y8
Y11
Y13
Y15
Y17
OE
GND
V
CC
GND
LE
GND
V
CC
GND
GND
3
NC
GND
V
CC
GND
4
GND
GND
V
CC
GND
5
NC
A2
A4
A6
A8
A11
A13
A15
A17
CLK
6
A1
A3
A5
A7
A9
A10
A12
A14
A16
A18
NC - No internal connection
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
(1)
LE
X
H
H
L
L
L
CLK
X
X
X
↑
↑
L or H
A
X
L
H
L
H
X
OUTPUT
Y
Z
L
H
L
H
Y
0 (1)
Output level before the indicated
steady-state input conditions were
established, provided that CLK is
high before LE goes low
2
www.ti.com
SN74ALVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES125J – FEBRUARY 1998 – REVISED NOVEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
27
CLK
30
LE
28
A1
54
1D
C1
CLK
3
Y1
To 17 Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Output voltage range
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through each V
CC
or GND
DGG package
θ
JA
Package thermal impedance
(4)
DGV package
DL package
GQL/ZQL package
T
stg
(1)
(2)
(3)
(4)
Storage temperature range
-65
V
I
< 0
V
O
< 0
-0.5
-0.5
-0.5
MAX
4.6
4.6
V
CC
+ 0.5
-50
-50
±50
±100
64
48
56
42
150
°C
°C/W
UNIT
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74ALVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES125J – FEBRUARY 1998 – REVISED NOVEMBER 2004
www.ti.com
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
V
CC
V
IH
Supply voltage
V
CC
= 1.65 V to 1.95 V
High-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 1.65 V to 1.95 V
V
IL
V
I
V
O
Low-level input voltage
Input voltage
Output voltage
V
CC
= 1.65 V
I
OH
High-level output current
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3 V
V
CC
= 1.65 V
I
OL
Low-level output current
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3 V
∆t/∆v
T
A
(1)
Input transition rise or fall rate
Operating free-air temperature
-40
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
0
0
1.65
0.65
×
V
CC
1.7
2
0.35
×
V
CC
0.7
0.8
3.6
V
CC
-4
-12
-12
-24
4
12
12
24
10
85
ns/V
°C
mA
mA
V
V
V
V
MAX
3.6
UNIT
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4
www.ti.com
SN74ALVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES125J – FEBRUARY 1998 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
I
OH
= -100
µA
I
OH
= -4 mA
I
OH
= -6 mA
V
OH
I
OH
= -12 mA
I
OH
= -24 mA
I
OL
= 100
µA
I
OL
= 4 mA
V
OL
I
OL
= 6 mA
I
OL
= 12 mA
I
OL
= 24 mA
I
I
I
OZ
I
CC
∆I
CC
C
i
C
o
(1)
Control inputs
Data inputs
Outputs
V
I
= V
CC
or GND
V
O
= V
CC
or GND
V
I
= V
CC
or GND,
One input at V
CC
- 0.6 V,
V
I
= V
CC
or GND
V
O
= V
CC
or GND
I
O
= 0
Other inputs at V
CC
or GND
TEST CONDITIONS
V
CC
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3V
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3.6 V
3.6 V
3.6 V
3 V to 3.6 V
3.3 V
3.3 V
3.5
5
7
MIN
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5
±10
40
750
µA
µA
µA
µA
pF
pF
V
V
TYP
(1)
MAX
UNIT
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
CC
= 1.8 V
MIN
f
clock
t
w
Clock frequency
Pulse duration
LE high
CLK high or low
Data before CLK↑
t
su
Setup time
Data before LE↓
Data after CLK↑
Data after LE↓
CLK high or low
CLK high
CLK low
(1)
(1)
(1)
(1)
(1)
(1)
(1)
V
CC
= 2.5 V
±
0.2 V
MIN
3.3
3.3
2.2
1.9
1.3
0.6
1.4
MAX
150
V
CC
= 2.7 V
MIN
3.3
3.3
2.1
1.6
1.1
0.6
1.7
MAX
150
V
CC
= 3.3 V
±
0.3 V
MIN
3.3
3.3
1.7
1.5
1
0.7
1.4
MAX
150
UNIT
MHz
ns
MAX
(1)
ns
t
h
Hold time
ns
(1)
This information was not available at the time of publication.
5
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