SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C − SEPTEMBER 1991 − REVISED MARCH 2003
D
Operating Voltage Range of 4.5 V to 5.5 V
D
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
D
Full Parallel Access for Loading
SN54BCT574 . . . J OR W PACKAGE
SN74BCT574 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54BCT574 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
V
CC
3D
4D
5D
6D
7D
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
2Q
3Q
4Q
5Q
6Q
TOP-SIDE
MARKING
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’BCT574 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PDIP − N
SOIC − DW
SOP − NS
SSOP − DB
CDIP − J
−55°C to 125°C
†
PACKAGE
†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74BCT574N
SN74BCT574DW
SN74BCT574DWR
SN74BCT574NSR
SN74BCT574DBR
SNJ54BCT574J
SNJ54BCT574W
SNJ54BCT574FK
0 C 70 C
0°C to 70°C
CFP − W
LCCC − FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
8D
GND
CLK
8Q
7Q
SN74BCT574N
BCT574
BCT574
BT574
SNJ54BCT574J
SNJ54BCT574W
SNJ54BCT574FK
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C − SEPTEMBER 1991 − REVISED MARCH 2003
description/ordering information (continued)
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q
0
Z
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, V
O
. . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA
Current into any output in the low state: SN54BCT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
†
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C − SEPTEMBER 1991 − REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54BCT574
MIN
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
A
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature
−55
4.5
2
0.8
−18
−12
48
125
0
NOM
5
MAX
5.5
SN74BCT574
MIN
4.5
2
0.8
−18
−15
64
70
NOM
5
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54BCT574
PARAMETER
V
IK
V
OH
V
CC
= 4.5 V,
V
CC
= 4.5 V
TEST CONDITIONS
I
I
= −18 mA
I
OH
= −3 mA
I
OH
= −12 mA
I
OH
= −15 mA
V
OL
I
I
I
IH
I
IL
I
OS
‡
SN74BCT574
MIN
2.4
2
TYP
†
3.3
V
3.1
0.42
0.4
20
−0.6
0.55
0.4
20
−0.6
−100
−225
50
−50
38.1
4.9
4.9
5.5
7.5
62
8
8
V
mA
µA
mA
mA
µA
µA
mA
mA
mA
pF
pF
0.55
MAX
−1.2
UNIT
V
−1.2
MIN
2.4
2
TYP
†
3.3
3.2
0.38
MAX
V
CC
= 4 5 V
4.5
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5.5 V,
V
CC
= 5 V,
V
CC
= 5 V,
I
OL
= 48 mA
I
OL
= 64 mA
V
I
= 5.5 V
V
I
= 2.7 V
V
I
= 0.5 V
V
O
= 0
V
O
= 2.7 V
V
O
= 0.5 V
Outputs open
Outputs open
Outputs open
V
I
= 2.5 V or 0.5 V
V
O
= 2.5 V or 0.5 V
−100
−225
50
−50
38.1
4.9
4.5
62
8
8
I
OZH
I
OZL
I
CCL
I
CCH
I
CCZ
C
i
C
o
†
‡
All typical values are at V
CC
= 5 V, T
A
= 25°C.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
CC
= 5 V,
T
A
= 25°C
MIN
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration, CLK high or low
High
Setup time data before CLK↑
time,
Hold time, data after CLK↑
Low
High or low
6.5
4.5
6
0
MAX
77
6.5
4.5
6
1
SN54BCT574
MIN
MAX
77
6.5
4.5
6
0
ns
ns
SN74BCT574
MIN
MAX
77
MHz
ns
UNIT
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C − SEPTEMBER 1991 − REVISED MARCH 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
CLK
OE
OE
Q
Q
Q
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 5 V,
T
A
= 25°C
MIN
77
2.2
2.8
2.5
3.7
1
1.3
6.5
6.1
6.4
7.3
4.4
4.2
8.6
8
8.1
9.2
7.4
5.8
TYP
MAX
SN54BCT574
MIN
77
2.2
2.8
2.5
3.7
1
1.3
11.2
9.7
10.9
11.3
8
7.1
MAX
SN74BCT574
MIN
77
2.2
2.8
2.5
3.7
1
1.3
10
8.9
10.4
10.9
7.5
6.4
ns
ns
ns
MAX
MHz
UNIT
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C − SEPTEMBER 1991 − REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
7 V (t
PZL
, t
PLZ
, O.C.)
Open
(all others)
S1
From Output
Under Test
C
L
(see Note A)
R1
Test
Point
R1
From Output
Under Test
C
L
(see Note A)
R2
R
L
= R1 = R2
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
1.5 V
t
w
0V
t
su
Data Input
(see Note B)
1.5 V
t
h
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
Low-Level
Pulse
1.5 V
1.5 V
0V
3V
1.5 V
0V
Timing Input
(see Note B)
3V
1.5 V
3V
Input
(see Note B)
t
PLH
In-Phase
Output
(see Note D)
t
PHL
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
3V
1.5 V
1.5 V
0V
t
PHL
V
OH
1.5 V
V
OL
t
PLH
V
OH
1.5 V
V
OL
t
PZH
Waveform 2
(see Notes C and D)
V
OH
1.5 V
0.3 V
0V
Waveform 1
(see Notes C and D)
Output
Control
(low-level enable)
t
PZL
1.5 V
1.5 V
1.5 V
0V
t
PLZ
3.5 V
V
OL
t
PHZ
0.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, t
r
= t
f
≤
2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
5
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