HB28J1000CFC/HB28J512CFC
HB28J256CFC/HB28J128CFC
CompactFlash
1 GByte/512 MByte/256 MByte/128 MByte
REJ03C0205-0100Z
Rev. 1.00
Mar. 16. 2004
Description
HB28J1000CFC, HB28J512CFC, HB28J256CFC, HB28J128CFC are CompactFlash
. This card complies
with CompactFlash
specification (CFA2.0), and is suitable for the usage of data storage memory medium
for PC or any other electric equipment and digital still camera. This card is equipped with 0.13
µm
CMOS
1Giga bit AG-AND Flash memory. This card is suitable for ISA (Industry Standard Architecture) bus
interface standard, and read/write unit is 1 sector (512 bytes) sequential access. By using this card it is
possible to operate good performance for the system which have CompactFlash
slots.
Notes: 1. CompactFlash
is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA
which in turn will license it royalty-free to CFA members.
*CFA: CompactFlash
Association.
2. These products are authorized for use in consumer applications such as digital still cameras.
Therefore, please contact Renesas Technology’s Sales Dept. before using these products in
industrial applications.
Features
•
CompactFlash
specification standard
50 pin two pieces connector and Type I (3.3 mm)
•
3.3 V / 5 V single power supply operation
•
Card density is 1 Giga bytes maximum
This card is equipped with 0.13
µm
CMOS 1 Giga bit AG-AND Flash memory
•
3 variations of mode access
Memory card mode
I/O card mode
True IDE mode
PIO mode4
Rev.1.00, Mar.16.2004, page 1 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
•
•
•
•
Internal self-diagnostic program operates at V
CC
power on
High reliability based on internal ECC (Error Correcting Code) function
Auto sleep mode
Data write is 100,000 cycles/block.*
1
Note: 1. One block consists of eight sectors (512 byte
×
8).
Card Line Up*
1
Type No.
Card density Capacity*
4
Total sectors/ Sectors/
card*
3
track*
2
63
63
48
32
Number of
head
16
16
15
8
Number of
cylinder
1987
993
695
978
HB28J1000CFC 1 GB
HB28J512CFC
HB28J256CFC
HB28J128CFC
Notes: 1.
2.
3.
4.
512 MB
256 MB
128 MB
1,025,482,752 byte 2,002,896
512,483,328 byte
256,204,800 byte
128,188,416 byte
1,000,944
500,400
250,368
These data are written in ID.
Total tracks = number of head
×
number of cylinder.
Total sectors/card = sectors/track
×
number of head
×
number of cylinder.
It is the logical address capacity including the area which is used for file system.
Rev.1.00, Mar.16.2004, page 2 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Card Pin Assignment
Memory card mode
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-OE
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
-CD2
-CD1
D11
D12
D13
D14
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O card mode
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-OE
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
-CD2
-CD1
D11
D12
D13
D14
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
True IDE mode
Signal name
GND
D3
D4
D5
D6
D7
-CS0
A10
-ATASEL
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
-CD2
-CD1
D11
D12
D13
D14
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
Rev.1.00, Mar.16.2004, page 3 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Memory card mode
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Note:
Signal name
D15
-CE2
-VS1
-IORD
-IOWR
-WE
RDY/-BSY
VCC
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
BVD2
BVD1
D8
D9
D10
GND
I/O
I/O
I
O
I
I
I
O
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O card mode
Signal name
D15
-CE2
-VS1
-IORD
-IOWR
-WE
-IREQ
VCC
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
D8
D9
D10
GND
I/O
I/O
I
O
I
I
I
O
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
True IDE mode
Signal name
D15
-CS1
-VS1
-IORD
-IOWR
-WE
INTRQ
VCC
-CSEL
-VS2
-RESET
IORDY
RFU*
1
RFU*
1
I/O
I/O
I
O
I
I
I
O
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
-DASP
-PDIAG
D8
D9
D10
GND
1. RFU is Reserved for Future Use.
Rev.1.00, Mar.16.2004, page 4 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Card Pin Explanation
Signal name
A10 to A0
(PC Card Memory
mode)
A10 to A0
(PC Card I/O mode)
A2 to A0
(True IDE mode)
BVD1
(PC Card Memory
mode)
-STSCHG
(PC Card I/O mode)
-PDIAG
(True IDE mode)
BVD2
(PC Card Memory
mode)
-SPKR
(PC Card I/O mode)
-DASP
(True IDE mode)
-CD1, -CD2
(PC Card Memory
mode)
-CD1, -CD2
(PC Card I/O mode)
-CD1, -CD2
(True IDE mode)
-CE1, -CE2
(PC Card Memory
mode)
Card Enable
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CS0, -CS1
(True IDE mode)
-CS1 is used for select the Alternate Status Register
and the Device Control Register -CS0 is the chip
select for the other task file registers.
I
7, 32
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte modes are defined by
combination of -CE1, -CE2 and A0.
O
26, 25
I/O
45
I/O
18, 19, 20
46
Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG is the Pass Diagnostic signal in
Master/Slave handshake protocol.
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CD1 and -CD2 are the card detection signals. -CD1
and -CD2 are connected to ground in this card, so
host can detect that the card is inserted or not.
Direction Pin No.
I
Description
8, 10, 11, 12, 14, Address bus is A10 to A0. A10 is MSB and A0 is
15, 16, 17, 18,
LSB.
19, 20
Rev.1.00, Mar.16.2004, page 5 of 65
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