CAT25C128/256
128K/256K-Bit SPI Serial CMOS EEPROM
FEATURES
s
5 MHz SPI Compatible
s
1.8 to 6.0 Volt Operation
s
Hardware and Software Protection
s
Low Power CMOS Technology
s
SPI Modes (0,0 &1,1)*
s
Commercial, Industrial and Automotive
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Self-Timed Write Cycle
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
s
64-Byte Page Write Buffer
s
Block Write Protection
Temperature Ranges
– Protect 1/4, 1/2 or all of EEPROM Array
DESCRIPTION
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS EEPROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface
and is enabled through a Chip Select (CS). In addition
to the Chip Select, the clock input (SCK), data in (SI)
and data out (SO) are required to access the device.
The
HOLD
pin may be used to suspend any serial
communication without resetting the serial sequence.
The CAT25C128/256 is designed with software and
hardware write protection features including Block Lock
protection. The device is available in 8-pin DIP, 8-pin
SOIC, 16-pin SOIC, 14-pin TSSOP and 20-pin TSSOP
packages.
PIN CONFIGURATION
SOIC Package
(S**, K, V**, X)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
BLOCK DIAGRAM
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TSSOP Package (U14, Y)** DIP Package (P, L)
CS
SO
NC
NC
NC
WP
VSS
V CC
HOLD
CS
SO
NC
WP
NC
VSS
NC
SCK
SI
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SOIC Package (S16, V)** TSSOP Package (U20, Y)**
CS
SO
NC
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
HOLD
NC
NC
NC
NC
SCK
SI
NC
CS
SO
SO
NC
NC
WP
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V CC
HOLD
HOLD
NC
NC
SCK
SI
NC
NC
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
EE PROM
ARRAY
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
NC
Function
Serial data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
1
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
* Other SPI modes available on request.
**CAT25C128 only.
Doc. No. 1018, Rev. H
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS1)
................... –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating
for extended periods may affect device performance
and reliability.
Max.
Units
Cycles/Byte
Years
Volts
mA
100,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
I
LO
V
IL(3)
V
IH(3)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
10
2
1
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
4.5V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
V
OUT
= 0V to V
CC
,
CS = 0V
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.0V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and
JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1018, Rev. G
2
CAT25C128/256
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
A.C. CHARACTERISTICS (CAT25C128)
Limits
Vcc=
1.8V-6.0V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
1000
1000
500
50
50
0
250
150
250
250
250
50
50
250
250
10
250
0
250
150
200
100
100
50
50
Min.
100
100
250
250
DC
1
50
2
2
250
250
10
250
0
100
50
Max.
V
CC
=
2.5V-6.0V
Min.
70
70
150
150
DC
3
50
2
2
40
40
5
80
Max.
V
CC
=
4.5V-5.5V
Min.
35
35
80
80
DC
5
50
2
2
Max.
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 50pF
Test
UNITS Conditions
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc No. 1018, Rev. H
CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256)
Limits
Vcc=
1.8V-6.0V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(3)
t
FI(3)
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
100
100
100
50
50
0
250
150
100
100
100
50
50
250
250
10
250
0
200
100
100
100
100
50
50
500
500
2500
2500
DC
0.2
100
2
2
100
100
10
200
0
200
100
100
100
100
50
50
V
CC
=
2.5V-6.0V
100
100
250
250
DC
2.0
50
2
2
V
CC
=
2.7V-6.0V
70
70
150
150
DC
2.5
50
2
2
100
100
10
200
VCC=
4.5V-5.5V
35
35
80
80
DC
5
50
2
2
40
40
5
80
0
100
50
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Min. Max. Min.
Max. Min.
Max. Min. Max. UNITS Conditions
C
L
= 50pF
NOTE:
(3) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1018, Rev. G
4
CAT25C128/256
FUNCTIONAL DESCRIPTION
The CAT25C128/256 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT25C128/256. During a read cycle, data
is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK.
CS
Chip Select
CS:
CS
is the Chip select pin.
CS
low enables the CAT25C128/
256 and
CS
high disables the CAT25C128/256.
CS
high
takes the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway). The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low transition
on
CS
is required prior to any sequence being initiated. A
low to high transition on
CS
after a valid write sequence is
what initiates an internal write cycle.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
t
HO
t
DIS
HI-Z
V
OH
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
5
Doc No. 1018, Rev. H
FPGA/CPLD
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