DATASHEET
82C37A
CMOS High PerformanceProgrammable DMA Controller
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either hardware
or software, and each channel is independently
programmable with a variety of features for flexible
operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
FN2967
Rev 4.00
October 2, 2015
Features
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with
Autoinitialization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10A Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
• Pb-Free Plus Anneal Available (RoHS Compliant)
FN2967 Rev 4.00
October 2, 2015
Page 1 of 26
82C37A
Ordering Information
PART NUMBER
5MHz
PART
MARKING
8MHz
PART
MARKING
12.5MHz
PART MARKING
TEMP
RANGE
(°C)
0 to +70
PKG.
DWG.
#
PACKAGE
40 Ld PDIP E40.6
CP82C37A-5
(No
CP82C37A-5
longer available,
recommended
replacement:
IS82C37A)
CS82C37A
CS82C37A
(No longer available,
recommended
replacement:
IS82C37A)
CS82C37AZ (Note 2) CS82C37AZ
(No longer available,
recommended
replacement:
IS82C37A)
IS82C37A-5
IS82C37A -5 IS82C37A
MD82C37A/B
5962-9054302MQA
NOTES:
1. Please refer to
TB347
for details on reel specifications.
IS82C37A
MD82C37A/B
5962-9054302MQA
CS82C37A-1296 CS82C37A -12
(Note 1)
(No
longer available,
recommended
replacement:
IS82C37A)
0 to +70
44 Ld PLCC N44.65
(Tape&Reel)
0 to +70
44 Ld PLCC N44.65
(Pb-Free)
-40 to +85 44 Ld PLCC N44.65
-55 to +125 40 Ld CDIP F40.6
SMD#
F40.6
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2967 Rev 4.00
October 2, 2015
Page 2 of 26
82C37A
Pinouts
82C37A (CERDIP)
(PDIP No longer available or supported)
TOP VIEW
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQ0
(GND) VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VCC
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
NC 7
NC 8
HLDA 9
ADSTB 10
AEN 11
HRQ 12
CS 13
CLK 14
RESET 15
DACK2 16
NC 17
18 19 20 21 22 23 24 25 26 27 28
DB7
DB6
DREQ3
DREQ2
DREQ1
DREQ0
DACK3
DB5
DACK1
DACK0
GND
82C37A (PLCC)
TOP VIEW
READY
MEMW
MEMR
EOP
39 A3
38 A2
37 A1
36 A0
35 VCC
34 DB0
33 DB1
32 DB2
31 DB3
30 DB4
29 NC
IOW
IOR
NC
A7
A6
A5
6
5
4
3
2
1 44 43 42 41 40
Block Diagram
EOP
RESET
CS
READY
CLK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DECREMENTOR
TEMP WORD
COUNT REG (16)
16-BIT BUS
16-BIT BUS
READ BUFFER
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
READ WRITE BUFFER
CURRENT
ADDRESS
(16)
CURRENT
WORD
COUNT
(16)
OUTPUT
BUFFER
INC/DECREMENTOR
TEMP ADDRESS
REG (16)
IO
BUFFER
A0 - A3
A4 - A7
A8 - A15
COMMAND
CONTROL
WRITE
BUFFER
DREQ0 -
DREQ3
HLDA
HRQ
DACK0 -
DACK3
4
4
READ
BUFFER
D0 - D1
REQUEST
(4)
MODE
(4 x 6)
STATUS
(8)
TEMPORARY
(8)
FN2967 Rev 4.00
October 2, 2015
Page 3 of 26
DB0 - DB7
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
COMMAND
(8)
MASK
(4)
INTERNAL DATA BUS
A4
IO
BUFFER
82C37A
Pin Description
SYMBOL
V
CC
GND
CLK
PIN
NUMBER
31
TYPE
DESCRIPTION
V
CC
: is the +5V power supply pin. A 0.1F capacitor between pins 31 and 20 is recommended for
decoupling.
Ground
I
CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations.
This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or
from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation.
CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU
communications.
RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.
READY: This signal can be used to extend the memory read and write pulses from the 82C37A to
accommodate slow memories or I/O devices. READY must not make transitions during its specified set-
up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition during
its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of
CLK, during which time HLDA must not transition.
DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs
used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and
DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK
will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes
these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ
will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low
(inactive) and the corresponding mask bit set.
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus.
The outputs are enabled in the Program condition during the I/O Read to output the contents of a register
to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is
programming the 82C37A control registers. During DMA cycles, the most significant 8-bits of the address
are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory
operations, data from the memory enters the 82C37A on the data bus during the read-from-memory
transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new
memory location.
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used
by the 82C37A to access data from the peripheral during a DMA Write transfer.
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control
signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
20
12
CS
11
I
RESET
13
I
READY
6
I
HLDA
7
I
DREQ0-
DREQ3
16-19
I
DB0-DB7
21-23
26-30
I/O
IOR
1
I/O
IOW
2
I/O
FN2967 Rev 4.00
October 2, 2015
Page 4 of 26
82C37A
Pin Description
SYMBOL
EOP
PIN
NUMBER
36
(Continued)
TYPE
I/O
DESCRIPTION
END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning
the completion of DMA services is available at the bidirectional EOP pin.
The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin low. A
pulse is generated by the 82C37A when terminal count (TC) for any channel is reached, except for
channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when
the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to
V
CC
.
When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate the
service, and if autoinitialize is enabled, the base registers will be written to the current registers of that
channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP
unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.
A0-A3
32-35
I/O
ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle,
they are inputs and are used by the 82C37A to address the control register to be loaded or read. In the
Active cycle, they are outputs and provide the lower 4-bits of the output address.
ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of address.
These lines are enabled only during the DMA service.
HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus. When
a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the 82C37A
issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted.
For stand-alone operation where the 82C37A always controls the busses, HRQ may be tied to HLDA.
This will result in one S0 state before the transfer.
DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one has
been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active
low.
ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits onto
the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.
AEN is active high.
ADDRESS STROBE: This is an active high signal used to control latching of the upper address byte. It
will drive directly the strobe input of external transparent octal latches, such as the 82C82. During block
operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding
operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C37A
clock.
MEMORY READ: The Memory Read signal is an active low three-state output used to access data from
the selected memory location during a DMA Read or a memory-to-memory transfer.
MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data to the
selected memory location during a DMA Write or a memory-to-memory transfer.
NO CONNECT: Pin 5 is open and should not be tested for continuity.
A4-A7
37-40
O
HRQ
10
O
DACK0-
DACK3
14, 15
24, 25
O
AEN
9
O
ADSTB
8
O
MEMR
3
O
MEMW
4
O
NC
5
FN2967 Rev 4.00
October 2, 2015
Page 5 of 26
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