SDRAM MODULE
KMM375S823CT SDRAM DIMM
Preliminary
KMM375S823CT
8Mx72 SDRAM DIMM with PLL & Register based on 8Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM375S823CT is a 8M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
KMM375S823CT consists of nine CMOS 8Mx8 bit Synchro-
nous DRAMs in TSOP-II 400mil packages, two 18-bits Drive
ICs for input control signal, one PLL in 24-pin TSSOP package
for clock and one 2K EEPROM in 8-pin TSSOP package for
Serial Presence Detect on a 168-pin glass-epoxy substrate.
Two 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each SDRAM. The
KMM375S823CT is a Dual In-line Memory Module and is
intented for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
FEATURE
• Performance range
Part No.
KMM375S823CT-G8
KMM375S823CT-GH
KMM375S823CT-GL
KMM375S823CT-G0
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V
±
0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height(1,500mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE
DQM0
Front
Pin
Front
Pin
Back
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
*CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
*CLK1
*A12
V
SS
CKE0
*CS3
DQM6
DQM7
*A13
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
*V
REF
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
*CLK3
NC
**SA0
**SA1
**SA2
V
DD
29 DQM1 57 DQ18 85
V
SS
58 DQ19 86 DQ32
30
CS0
59
31
DU
V
DD
87 DQ33
60 DQ20 88 DQ34
V
SS
32
61
A0
33
NC
89 DQ35
62 *V
REF
90
34
A2
V
DD
63 *CKE1 91 DQ36
35
A4
64
A6
36
V
SS
92 DQ37
65 DQ21 93 DQ38
37
A8
38 A10/AP 66 DQ22 94 DQ39
67 DQ23 95 DQ40
39
BA1
68
V
DD
40
V
SS
96
V
SS
69 DQ24 97 DQ41
V
DD
41
42 CLK0 70 DQ25 98 DQ42
71 DQ26 99 DQ43
V
SS
43
72 DQ27 100 DQ44
44
DU
73
45
CS2
V
DD
101 DQ45
46 DQM2 74 DQ28 102 V
DD
47 DQM3 75 DQ29 103 DQ46
76 DQ30 104 DQ47
DU
48
77 DQ31 105 CB4
V
DD
49
78
NC
50
V
SS
106 CB5
79 *CLK2 107 V
SS
NC
51
80
CB2
52
NC
108
NC
81 NC/WP 109
CB3
53
NC
82 **SDA 110 V
DD
V
SS
54
55 DQ16 83 **SCL 111 CAS
56 DQ17 84
V
DD
112 DQM4
PIN NAMES
Pin Name
A0 ~ A11
BA0~BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
CKE0
CS0, CS2
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
*V
REF
REGE
SDA
SCL
SA0 ~ 2
DU
NC
WP
Function
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address storbe
Colume address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Register enable
Serial data I/O
Serial clock
Address in EEPROM
Don′t use
No connection
Write protection
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 2 Jan 1999
SDRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Preliminary
KMM375S823CT
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V
CC
through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
V
DD
/V
SS
Data input/output
Check bit
Power supply/ground
REV. 2 Jan 1999
SDRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
BCKE0
B
0
A0~B
0
A11,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
10Ω
Preliminary
KMM375S823CT
•
•
•
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D0
•
•
•
D1
DQ8~15
10Ω
PCLK1
•
•
•
•
•
•
D2
BDQM1
CB0~7
10Ω
BCS2
•
BDQM2
DQ16~23
10Ω
PCLK3
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D3
•
•
•
D4
BDQM3
DQ24~31
10Ω
•
BDQM4
DQ32~39
10Ω
•
D5
•
BDQM5
DQ40~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
•
•
•
BDQM6
DQ48~55
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D7
D8
BDQM7
DQ56~63
10Ω
V
SS
Vcc
A0~A9
RAS,CAS,WE
DQM0,1,4,5
CS0
REGE
PCLK2
10kΩ
10pF
Vcc
A10,A11,BA0~1
CS2
CKE0
DQM2,3,6,7
SN74ALVC162836
B
0
A10,B
0
A11,BBA0~1
BCS2
BCKE0
BDQM2,3,6,7
SN74ALVC162836
B
0
A0~B
0
A9
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
LE
CLK0
OE
10pF
10Ω
CLK
FIBIN
2G
AGND
1G
AVCL
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
CDC2509A
PCLK0
PCLK1
PCLK2
PCLK3
FBOUT
Serial PD
SCL
WP
47KΩ
A0
A1
A2
SDA
LE
OE
SA0 SA1 SA2
REV. 2 Jan 1999
SDRAM MODULE
Preliminary
KMM375S823CT
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
*1
Control Signal(RAS,CAS,WE)
REG
*3
D
8
9
10
11
OUT
*1. Register Input
0
CLK
1
2
3
4
5
6
7
12
13
14
15
16
17
18
19
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
tSAC
tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Read
Command
Precharge
Command
Row Active
Write
Command
Precharge
Command
td, tr = Delay of register (SN74ALVC162836)
Notes :
1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (SN74ALVC162836). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D
IN
is to be issued 1clock after write command in external timing because D
IN
is issued directly to module.
: Don
′t
care
REV. 2 Jan 1999
SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
50
Preliminary
KMM375S823CT
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current (Inputs)
Input leakage current (I/O Pins)
Symbol
V
DD
V
IH
V
IL
V
OH
V
OL
I
IL
I
IL
Min
3.0
2.0
-0.3
2.4
-
-2
-1.5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
2
1.5
Unit
V
V
V
V
V
uA
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
3,4
Note
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
C
OUT1
Min
-
-
-
-
-
-
-
-
-
Max
16
16
16
26
16
16
16
17
17
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Parameter
Input capacitance (A
0
~ A
11
)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
Input capacitance (CLK0)
Input capacitance (CS0, CS2)
Input capacitance (DQM0 ~ DQM7)
Input capacitance (BA0 ~ BA1)
Data input/output capacitance (DQ0 ~ DQ63)
Data input/output capacitance (CB0 ~ CB7)
REV. 2 Jan 1999
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