RAiO
RA8835A
Dot Matrix
LCD Controller
Specification
Version 1.0
February 7, 2007
RAiO Technology Inc.
©Copyright
RAiO Technology Inc. 2006, 2007
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RA8835A
Preliminary Version 1.0
Dot Matrix LCD Controller
1. Overview
The RA8835A is a controller IC that can display text and graphics on LCD panel. It can display layered text and
graphics, scroll the display in any direction and partition the display into multiple screens. It also stores text,
character codes and bitmapped graphics data in external frame buffer memory. Display controller functions
include transferring data from the controlling microprocessor to the buffer memory, reading memory data,
converting data to display pixels and generating timing signals for the buffer memory, LCD panel.
The RA8835A has an internal character generator with 160, 5 X
7 pixel characters in internal mask ROM. The
character generators support up to 64, 8 X
16 pixel characters in external character generator RAM and up to
256, 8 X
16 pixel characters in external character generator ROM.
2. Features
Text, graphics and combined text/graphics
display modes
Three overlapping screens in graphics mode
Up to 640 X
256 pixel LCD panel display
resolution
Programmable cursor control
Smooth horizontal and vertical scrolling of all or
part of the display
1/2-duty to 1/256-duty LCD drive
Up to 640 X
256 pixel LCD panel display
resolution memory
160, 5 X
7 pixel characters in internal mask-
programmed character generator ROM
Up to 64, 8 X 16 pixel characters in external
character generator RAM
Up to 256, 8 X 16 pixel characters in external
character generator ROM
6800 and 8080 family microprocessor interfaces
Low power consumption—3.5 mA operating
current (V
DD
= 3.5V), 0.05
μA
standby current
Package:
RA8835AP3N: QFP-60 pin (Lead Free)
RA8835AP4N: TQFP-60 pin (Lead Free)
Power: 2.7 to 5.5 V
3. Block Diagram
V A [1 5 :0 ], V D [7 :0 ],
VCE, VRD, VW R
TEST
2 5 6 B yte
CGROM
D is p la y R A M
I/F
S ys te m
C o n f ig u r e
R e g is t e r s
B lo c k
C u rs o r
C o n t r o lle r
D a ta
L a tc h
MCU
I/F
X ’t a l
OSC
T im in g
G e n e ra to r
D [7 :0 ], C S , R D , W R
A0, R ES, SEL1, SEL2
XD
XG
Y D IS , L P , W F , X S C L ,
Y D , Y S C L , X D [3 :0 ]
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RA8835A
Preliminary Version 1.0
Dot Matrix LCD Controller
4. Package
XG
SEL1
SEL2
WR
RD
NC
NC
RES
VRD
VCE
VWR
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VD4
VD5
VD6
VD7
YSCL
YD
YDIS
WF
LP
GND
XSCL
SECL
XD0
XD1
XD2
XD
CS
A0
VDD
D0
D1
D2
D3
D4
D5
D6
50
45
40
35
RAiO
60
1
Index
TM
30
VA8
VA9
VA10
VA11
VA12
VA13
NC
VA14
VA15
VD0
VD1
VD2
45
RA8835AP3N
07xx
Date Code(Year 2007)
29
5
6
25
20
10
15
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
VA7
VA6
NC
46
31
30
RAiO
TM
RA8835AP4N
07xx
Index
60
1
Date Code(Year 2007)
16
15
XD3
D7
D6
D5
D4
D3
D2
D1
D0
VDD
A0
CS
XD
XG
SEL1
D7
XD3
XD2
XD1
XD0
XECL
XSCL
GND
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3
Figure 4-1: RA8835AP3N(QFP-60 Pin)
Figure 4-2: RA8835AP4N (TQFP-60 Pin)
5. Pin Descriptions
5.1.1. MCU Interface
Pin Name
D0 to D7
Function
MCU Data Bus.
Tri-state input/output pins. Connect these pins to an 8- or 16-bit microprocessor
bus.
MCU Interface Select.
The RA8835A series supports both 8080 family processors (such as the 8085
and Z80®) and 6800 family processors (such as the 6802 and 6809).
SEL1
SEL1,
SEL2
0
1
SEL2*
0
0
Interface
8080
family
6800
family
A0
A0
A0
RD
WR
SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does
appear on SEL1, decouple it to ground using a capacitor placed as close to the
pin as possible.
Read Control or Enable.
When the 8080 family interface is selected, this signal acts as the active-LOW
read strobe. The RA8835A series output buffers are enabled when this signal is
active.
When the 6800 family interface is selected, this signal acts as the active-HIGH
enable clock.
Data is read from or written to the RA8835A series when this clock goes HIGH.
RD
or
E
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VA5
VA4
VA3
VA2
VA1
VA0
VWR
VCE
VRD
RES
NC
NC
RD
WR
SEL2
CS
CS
CS
RD
WR
E
R/
W
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RA8835A
Preliminary Version 1.0
Dot Matrix LCD Controller
Write Control or Read/Write Control.
When the 8080 family interface is selected, this signal acts as the active-LOW
write strobe. The bus data is latched on the rising edge of this signal.
When the 6800 family interface is selected, this signal acts as the read/write
control signal. Data is read from the RA8835A series if this signal is HIGH, and
written to the RA8835A series if it is LOW.
Chip Select.
This active-LOW input enables the RA8835A series. It is usually connected to
the output of an address decoder device that maps the RA8835A series into the
memory space of the controlling microprocessor.
Command/Data Select.
8080 Family Interface:
A0
0
1
0
1
A0
RD
0
WR
1
WR
or
R/
W
CS
0
1
1
1
0
0
Function
Status flag read
Display data and cursor address
read
Display data and parameter write
Command write
6800 Family Interface:
A0
0
1
0
1
R/
W
1
1
0
0
E
1
1
1
1
Function
Status flag read
Display data and cursor address
read
Display data and parameter write
Command write
RES
Hardware Reset.
This active-LOW input performs a hardware reset on the RA8835A series. It is an
Schmitt-trigger input for enhanced noise immunity; however, care should be taken
to ensure that it is not triggered if the supply voltage is lowered.
5.1.2 Display Memory Control
The RA8835A series can directly access static RAM and PROM. The designer may use a mixture of
these two types of memory to achieve an optimum trade-off between low cost and low power
consumption.
Pin Name
Function
16-bit Display Memory Address.
When accessing character generator RAM or ROM, VA0 to VA3, reflect the
lower 4 bits of the RA8835A row counter.
Display Memory Data Bus.
8-bit tri-state display memory data bus. These pins are enabled when
VRD
or
VWR
is LOW.
Display Memory Write Control.
Active-LOW display memory write control output.
Display Memory Read Control.
Active-LOW display memory read control output.
VA0 to VA15
VD0 to VD7
VWR
VRD
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RA8835A
Preliminary Version 1.0
Dot Matrix LCD Controller
VCE
Display Memory Chip Select.
Active-LOW static memory standby control signal. VCE can be used with CS .
5.1.3 LCD Drive Signals
In order to provide effective low-power drive for LCD matrixes, the RA8835A series can directly
control both the X- and Y-drivers using an enable chain.
Pin Name
Function
Data Output for Driver.
4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs
of the X-driver chips.
Latch Clock.
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift
registers of the X-drivers. To conserve power, this clock halts between LP and
the start of the following display line (See section 6.3.7).
Trigger Clock for Chain Cascade.
The falling edge of XECL triggers the enable chain cascade for the X-drivers.
Every 16th clock pulse is output to the next X-driver.
Latch Pulse.
LP latches the signal in the X-driver shift registers into the output data latches.
LP is a falling-edge triggered signal, and pulses once every display line.
Connect LP to the Y-driver shift clock on modules.
AC Drive Output.
The WF period is selected to be one of two values with SYSTEM SET
command.
Latch Clock for YD.
The falling edge of YSCL latches the data on YD into the input shift registers of
the Y-drivers. YSCL is not used with driver ICs which use LP as the Y-driver
shift clock.
Data Pulse Output for Y Drivers.
It is active during the last line of each frame, and is shifted through the Y drivers
one by one (by YSCL), to scan the display’s common connections.
Power-down Output Signal.
YDIS is HIGH while the display drive outputs are active. YDIS goes LOW one or
two frames after the sleep command is written to the RA8835A series. All Y-
driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in
the LCD unit, the LCD power drive supplies must also be disabled when the
display is disabled by YDIS.
XD0 to XD3
XSCL
XECL
LP
WF
YSCL
YD
YDIS
5.1.4. Oscillator and Power
Pin Name
Function
Crystal Connection for Internal Oscillator
This pin can be driven by an external clock source that satisfies the timing
specifications of the EXT f0 signal (See section 7.3.6).
Crystal Connection for Internal Oscillator
Leave this pin open when using an external clock source.
2.7 to 5.5V Supply.
This may be the same supply as the controlling microprocessor.
XG
XD
VDD
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