MIC2589/MIC2595
Single-Channel, Negative High-Voltage Hot
Swap Power Controller/Sequencer
General Description
The MIC2589 and MIC2595 are single-channel,
negative voltage hot swap controllers designed to
address the need for safe insertion and removal of
circuit boards into “live” system backplanes, while using
few external components. The MIC2589/MIC2589R and
the MIC2595/MIC2595R are each available in 14-pin
SOIC packaging and work in conjunction with an
external N-Channel MOSFET for which the gate drive is
controlled to provide inrush current limiting and output
voltage slew-rate control. Overcurrent fault protection is
also provided via a programmable overcurrent threshold
and filter. Very fast fault response is provided to ensure
that system power supplies maintain regulation even
during output short circuits. These controllers offer two
responses to a circuit breaker fault condition: the
MIC2589 and MIC2595 latch the circuit breaker’s output
off when the overcurrent threshold interval is exceeded
and the overcurrent filter times out while the MIC2589R
and MIC2595R automatically attempt to restart at a fixed
duty cycle after a current limit fault. A primary Power-
Good signal and two secondary (delayed and
staggered) Power-Good signals are provided to indicate
that the output voltage is within its valid operating range.
These signals can be used to perform an all-at-once or
a sequenced enabling of one or more DC-DC power
modules.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
Features
•
Provides safe insertion and removal from live –48V
(nominal) backplanes
•
Operates from –19V to –80V
•
Fast responding circuit breaker (<1µs) to short circuit
conditions
•
User-programmable overcurrent detector response
time
•
Electronic circuit breaker function:
Output latch OFF (MIC2589/MIC2595)
Output auto-retry (MIC2589R/MIC2595R)
•
Active current regulation to control inrush currents
•
Programmable undervoltage and overvoltage
lockouts (MIC2589/MIC2589R)
•
Programmable UVLO hysteresis
(MIC2595/MIC2595R)
•
Staggered ‘Power-Good’ output signals provide load
sequencing
Active-HIGH (-1)
Active-LOW (-2)
Applications
•
•
•
•
Central office switching
–48V power distribution
Distributed power systems
AdvancedTCA
_________________________________________________________________________________________________________
Ordering Information
Part Number
Standard
MIC2589-1BM
MIC2589-2BM
MIC2589R-1BM
MIC2589R-2BM
MIC2595-1BM
MIC2595-2BM
MIC2595R-1BM
MIC2595R-2BM
Pb-Free
MIC2589-1YM
MIC2589-2YM
MIC2589R-1YM
MIC2589R-2YM
MIC2595-1YM
MIC2595-2YM
MIC2595R-1YM
MIC2595R-2YM
PWRGD
Polarity
Active-High
Active-Low
Active-High
Active-Low
Active-High
Active-Low
Active-High
Active-Low
Lockout Functions
Programmable UVLO & OVLO
Programmable UVLO & OVLO
Programmable UVLO & OVLO
Programmable UVLO & OVLO
Programmable UVLO Hysteresis
Programmable UVLO Hysteresis
Programmable UVLO Hysteresis
Programmable UVLO Hysteresis
Circuit Breaker
Function
Latched Off
Latched Off
Auto Retry
Auto Retry
Latched Off
Latched Off
Auto Retry
Auto Retry
Package
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
December 2005
M9999-120505
(408) 955-1690
Micrel
MIC2589/MIC2595
Typical Applications
-48V RTN
(Long Pin)
*D1
SMAT70A
MIC2589-2BM
VDD
/PWRGD1
PGTIMER
UV
OV
CFILTER
CNLD
VEE
/PWRGD3
/PWRGD2
DRAIN
GATE
SENSE
N/C
-48V RTN
1
14
-48V RTN
(Short Pin)
R1
689k
1%
R2
11.8k
1%
C
TIMER
0.068µF
2
13
C4
100µF
IN+
C3
0.1µF
OUT+
+5V
OUT
ON/OFF*
IN–
OUT–
+5V RTN
3
12
4
11
C1
0.47µF
R3
12.4k
1%
C
FILTER
2.2µF
5
10
IN+
C6
100µF
*C2
0.1µF
R4
10
C8
100µF
C7
0.1µF
C5
0.1µF
OUT+
+2.5V
OUT
6
9
ON/OFF*
IN–
OUT–
+2.5V RTN
C
NLD
0.068µF
7
8
IN+
OUT+
+1.8V
OUT
ON/OFF*
IN–
OUT–
+1.8V RTN
-48V RTN
(Long Pin)
Nominal Undervoltage and Overvoltage Thresholds:
V
UV
=36.5V
V
OV
=71.2V
Overcurrent TImer Delay
=30ms
t
FLT
~
*Optional components (See Funtional Description and Applications Information for more details)
#An external pull-up resistor for the power-good signal is necessary for DC-DC convertors (and all other load modules) not equipped with an
internal pull-up impedance
R
SENSE
0.01
5%
M1
SUM110N10-09
December 2005
2
M9999-120505
(408) 955-1690
Micrel
MIC2589/MIC2595
Pin Configuration
14-Pin SOIC
MIC2589-1BM
MIC2589R-1BM
MIC2589-1YM
MIC2589R-1YM
14-Pin SOIC
MIC2589-2BM
MIC2589R-2BM
MIC2589-2YM
MIC2589R-2YM
14-Pin SOIC
MIC2595-1BM
MIC2595R-1BM
MIC2595-1YM
MIC2595R-1YM
14-Pin SOIC
MIC2595-2BM
MIC2595R-2BM
MIC2595-2YM
MIC2595R-2YM
December 2005
3
M9999-120505
(408) 955-1690
Micrel
MIC2589/MIC2595
Pin Description
Pin Number
1
Pin Name
PWRGD1
(MIC25XX-1)
Active High
/PWRGD1
(MIC25XX-2)
Active Low
2
PGTIMER
Pin Function
Power-Good Output 1: Asserted when the voltage on the DRAIN pin (V
DRAIN
) is within
V
PGTH
of VEE, indicating that the output voltage is within proper specifications. For
the MIC2589-1 and MIC2595-1, PWRGD1 will be high impedance when V
DRAIN
is
less than V
PGTH
, and will pull-down to V
DRAIN
when V
DRAIN
is greater than V
PGTH
. For
the MIC2589-2 and MIC2595-2, /PWRGD1 will pull-down to V
DRAIN
when V
DRAIN
is
less than V
PGTH
, and will be high-impedance when V
DRAIN
is greater than V
PGTH
.
A capacitor connected from this pin to VEE sets the time interval between assertions
of PWRGD2 (or /PWRGD2) and PWRGD3 (or /PWRGD3) relative to PWRGD1 (or
/PWRGD1). See the “Functional Description” for further detail.
Undervoltage Threshold Input: When the voltage at the UV pin is less than the V
UVL
threshold, the GATE pin is immediately pulled low by an internal 100µA current pull-
down. The UV pin is also used to cycle the device off and on to reset the circuit
breaker. Taken together, the OV and UV pins form a window comparator that defines
the limits of V
EE
to deliver power to the load.
Turn-Off Threshold: When the voltage at the OFF pin is less than the V
OFFL
threshold, the GATE pin is immediately pulled low by an internal 100µA current pull-
down. The OFF pin is also used to cycle the device off and on to reset the circuit
breaker. Taken together, the ON and OFF pins provide programmable hysteresis for
the MIC2595 to be enabled.
Overvoltage Threshold Input: When the voltage at the OV pin is greater than the
V
OVH
threshold, the GATE pin is immediately pulled low by an internal 100µA current
pull-down.
3
UV
(MIC2589
and
MIC2589R)
3
OFF
(MIC2595
and
MIC2595R)
OV
(MIC2589
and
MIC2589R)
4
4
ON
(MIC2595
and
MIC2595R)
CFILTER
Turn-On Threshold: At initial system power-up or after the part has been shut off by
the OFF pin, the voltage on the ON pin must be above the V
ONH
threshold in order for
the MIC2595 to be enabled.
Current Limit Response Timer: A capacitor connected between this pin and VEE
provides filtering against nuisance tripping of the circuit breaker by setting a time
delay, t
FLT
, for which an overcurrent event must last prior to signaling a fault condition
and latching the output off. The minimum time for t
FLT
will be the time it takes for the
output (capacitance) to charge to VEE during start-up. This pin is held to VEE with a
3µA current pull-down when no current limit condition exists. See the “Functional
Description” for further details.
No-Load Detect Timer: The absence of a load for the MIC2589/MIC2589R is defined
for any current load that is less than 20% of the full-scale current limit (i.e., 0.20
×
I
LIM
). A capacitor between CNLD and VEE sets the filter delay, t
NLD
, for a load current
that is 80% (or greater) below the full-scale current limit before the circuit breaker is
tripped.
Negative Supply Voltage Input: Connect the negative, or low side, terminal of the
input power supply.
No Internal Connection
Circuit Breaker Sense Input: A resistor between this pin and VEE sets the current
limit trip point for the circuit. When the current limit threshold of IR = 50mV is
exceeded for t
FLT
, the circuit breaker is tripped and the GATE pin is immediately
pulled low by I
GATEOFF
. Toggling UV or OV will reset the circuit breaker. In order to
disable the circuit breaker (i.e., eliminate overcurrent V
SENSE
-V
EE
protection), connect
(short) the SENSE pin to VEE and also connect the CNLD pin to VEE to disable the
no-load detection feature.
Gate Drive Output: Connects to the Gate of an N-Channel MOSFET.
Drain Sense Input: Connects to the Drain of an N-Channel MOSFET.
5
6
CNLD
7
8
9
VEE
NC
SENSE
10
11
GATE
DRAIN
December 2005
4
M9999-120505
(408) 955-1690
Micrel
MIC2589/MIC2595
Pin Desription (cont.)
Pin Number
12
Pin Name
PWRGD2
(MIC25XX-1)
Pin Function
Power-Good Output 2: Asserted when the following is true: (PWRGD1 = Asserted)
AND (Time after Assertion of PWRGD1 = Time PWRGD2, as programmed by the
capacitor on PGTIMER). Once PWRGD1 is asserted, the PGTIMER pin begins to
charge and PWRGD2 will assert when PGTIMER crosses the PWRGD2 threshold
(V
THRESH(PG2)
= 0.63V, typical). Also see PWRGD1 and PGTIMER pin descriptions
/Power-Good Output 2: Asserted when the following is true: (/PWRGD1 = Asserted)
AND (Time after Assertion of /PWRGD1 = Time /PWRGD2, as programmed by the
capacitor on PGTIMER). Once /PWRGD1 is asserted, the PGTIMER pin begins to
charge and /PWRGD2 will assert when PGTIMER crosses the /PWRGD2 threshold
(V
THRESH(PG2)
= 0.63V, typical). Also see /PWRGD1 and PGTIMER pin descriptions.
Power-Good Output 3: Asserted when the following is true: (PWRGD1 = Asserted)
AND (Time after Assertion of PWRGD1 = Time PWRGD3, as programmed by the
capacitor on PGTIMER). Once PWRGD1 is asserted, the PGTIMER pin begins to
charge and PWRGD3 will assert when PGTIMER crosses the PWRGD3 threshold
(V
THRESH(PG3)
= 1.15V, typical). Also see PWRGD1 and PGTIMER pin descriptions.
/Power-Good Output 3: Open Collector. Asserted when the following is true:
(/PWRGD1 = Asserted) AND (Time after Assertion of /PWRGD1 = Time /PWRGD3,
as programmed by the capacitor on PGTIMER). Once /PWRGD1 is asserted, the
PGTIMER pin begins to charge and /PWRGD3 will assert when PGTIMER crosses
the /PWRGD3 threshold (V
THRESH(PG3)
= 1.15V, typical). Also see /PWRGD1 and
PGTIMER pin descriptions.
Positive Supply Input: Connect to the positive, or high side, terminal of the input
power supply.
12
/PWRGD2
(MIC25XX-2)
13
PWRGD3
(MIC25XX-1)
13
/PWRGD3
(MIC25XX-2)
14
VDD
December 2005
5
M9999-120505
(408) 955-1690
FPGA/CPLD
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