SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
D
D
D
D
D
D
D
8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
Asynchronous Parallel Clear
Active-High Decoder
Enable Input Simplifies Expansion
Expandable for n-Bit Applications
Four Distinct Functional Modes
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
SN54HC259 . . . J OR W PACKAGE
SN74HC259 . . . D, N, OR PW PACKAGE
(TOP VIEW)
S0
S1
S2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLR
G
D
Q7
Q6
Q5
Q4
SN54HC259 . . . FK PACKAGE
(TOP VIEW)
description
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches, and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs.
In the addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all
unaddressed latches remaining in their previous
states. In the memory mode, all latches remain in
their previous states and are unaffected by the
data or address inputs. To eliminate the possibility
of entering erroneous data in the latches, G
should be held high (inactive) while the address
lines are changing. In the 1-of-8 decoding or
demultiplexing mode, the addressed output
follows the level of the D input with all other
outputs low. In the clear mode, all outputs are low
and unaffected by the address and data inputs.
S2
Q0
NC
Q1
Q2
4
5
6
7
8
S1
S0
NC
V
CC
CLR
3
2 1 20 19
18
17
16
15
14
9 10 11 12 13
G
D
NC
Q7
Q6
NC – No internal connection
The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC259 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Q3
GND
NC
Q4
Q5
1
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
logic symbol, each internal latch
D
C
R
1D
C1
1R
Q
logic diagram, each internal latch (positive logic)
C
D
C
C
TG
Q
C
C
C
TG
R
C
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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