EH4600ETTS-45.000M TR
EH46 00 ET
Series
RoHS Compliant (Pb-free) 3.3V 4 Pad 2.5mm x 3.2mm
Ceramic SMD LVCMOS Oscillator
Frequency Tolerance/Stability
±100ppm Maximum
Operating Temperature Range
-40°C to +85°C
Duty Cycle
50 ±10(%)
RoHS
Pb
Packaging Options
Tape & Reel
TS -45.000M TR
Nominal Frequency
45.000MHz
Pin 1 Connection
Tri-State (High Impedance)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
45.000MHz
±100ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°,
260°C Reflow, Shock, and Vibration)
±5ppm/Year Maximum
-40°C to +85°C
3.3Vdc ±5%
12mA Maximum (No Load)
90% of Vdd Minimum (IOH = -8mA)
10% of Vdd Maximum (IOL = +8mA)
6nSec Maximum (Measured at 20% to 80% of waveform)
50 ±10(%) (Measured at 50% of waveform)
30pF Maximum
CMOS
Tri-State (High Impedance)
90% of Vdd Minimum or No Connect to Enable Output, 10% of Vdd Maximum to Disable Output (High
Impedance)
10µA Maximum (Pin 1 = Ground)
±100pSec Maximum
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Standby Current
Absolute Clock Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500Vdc
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev A 8/14/2010 | Page 1 of 6
EH4600ETTS-45.000M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% of Waveform
50% of Waveform
20% of Waveform
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency
ceramic bypass capacitor close (less than 2mm) to the package ground and supply voltage
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev A 8/14/2010 | Page 3 of 6
EH4600ETTS-45.000M TR
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
High Temperature Infrared/Convection
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
3°C/second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev A 8/14/2010 | Page 5 of 6
FPGA/CPLD
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