The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10 ns with output enable access times (t
OE
) of 5 ns are ideal for high-
performance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle
2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable
(OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in
common industry standard packages
.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–55
–55
–
Max
+4.60
V
CC
+0.50
1.25
+125
+125
50
Unit
V
V
W
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
L
L
L
L
L
WE
X
H
H
H
L
L
L
H
X
OE
X
L
L
L
X
X
X
H
X
LB
X
L
H
L
L
L
H
X
H
UB
X
H
L
L
L
H
L
X
H
I/O0–I/O7
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
High Z
High Z
I/O8–I/O15
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
D
IN
High Z
Mode
Standby (I
SB
), I
SBI
)
Read I/O0–I/O7 (I
CC
)
Read I/O8–I/O15 (I
CC)
Read I/O0–I/O15 (I
CC
)
Write I/O0–I/O15 (I
CC
)
Write I/O0–I/O7 (I
CC
)
Write I/O8–I/O15 (I
CC
)
Output disable (I
CC
)
Key:
H = high, L = low, X = don’t care.
9/20/06, v 1.0
Alliance Memory
P. 2 of 10
AS7C31026C
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature (industrial)
V
IL
= -2.0V for pulse width less than 5ns, once per cycle.
V
IH =
V
CC
+2.0V for pulse width less than 5ns, once per cycle.
Symbol
V
CC
V
IH
V
IL
T
A
Min
3.0
2.0
–0.5
–40
Nominal
3.3
–
–
–
Max
3.6
V
CC
+ 0.5
0.8
85
Unit
V
V
V
o
C
DC operating characteristics (over the operating range)
1
AS7C31026C-10
Parameter
Input leakage current
Sym
|
I
LI
|
|
I
LO
|
Test conditions
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max
CE = V
IH
,
V
OUT
= GND to V
CC
V
CC
= Max,
CE
≤
V
IL
, I
OUT
= 0mA
f = f
Max
V
CC
= Max,
CE
≥
V
IH
, f = f
Max
V
CC
= Max, CE
≥
V
CC
–0.2 V,
V
IN
≤
0.2 V or
V
IN
≥
V
CC
–0.2 V, f = 0
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Min
–
Max
5
Unit
µA
Output leakage current
–
5
µA
Operating power supply current
I
CC
I
SB
–
160
mA
–
45
mA
Standby power supply current
I
SB1
V
OL
V
OH
–
–
2.4
10
0.4
–
mA
V
V
Output voltage
Capacitance (f = 1MHz, T
a
= 25
°C,
V
CC
= NOMINAL)
2
Parameter
Input capacitance
Symbol
C
IN
Signals
A, CE, WE, OE, LB, UB
Test conditions
V
IN
= 0 V
V
IN
= V
OUT
= 0 V
Max
6
7
Unit
pF
pF
I/O capacitance
C
I/O
I/O
Note:
1. This parameter is guaranteed by device characterization, but is not production tested.
FPGA/CPLD
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