DA9181.006
13 October, 1999
The MAS9181 comprises eight digital to analog
2
converters (DACs) each controlled by a two-wire I C
bus. The DACs are individually programmed using an 8-
bit word to select an output from one of 256 voltage
steps. The maximum output voltage of all DACs is set
· Rail to rail output stages
· Octal 8-bit DACs on a single monolithic chip
· Power supply range from +5 V to +12 V
· -20°C to +85°C temperature range
· 16-pin PDIL and SO package
· Power-up reset
SDA
SCL
A0
A1
A2
I C Bus
Slave
Receiver
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
Reference
Voltage
Generator
8-BIT DAC
8-BIT DAC
VDD GND
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· Trimmer replacement
· AGC/AFT or TVs and VCRs
· Graphic equalizers
· High resolution monitors
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by Vmax and the resolution is Vmax/256. At power-on all
2
outputs are set to their lowest value. The I C-bus slave
receiver has 3 programmable address pins (2 for
MAS9181 CS).
iEEPCi
8-BIT DAC
DAC7
8-BIT DAC
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
1
DA9181.006
13 October, 1999
VDD
1
2
3
4
5
6
7
8
9
1
2
3
4
6
7
P
I
I/O
I
I
I
I
G
O
O
O
O
O
O
O
O
Positive supply voltage
Control input for DAC maximum output voltage
I C bus serial data input/output
I C bus serial data clock
Programmable address bits for I C bus slave receiver
Programmable address bits for I C bus slave receiver
Programmable address bits for I C bus slave receiver
Ground
Analog voltage output
Analog voltage output
Analog voltage output
Analog voltage output
Analog voltage output
Analog voltage output
Analog voltage output
Analog voltage output
2
2
2
2
2
Vmax
SDA
SCL
A
0
A
1
A
2
GND
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
*1 MAS9181BN (PDIP16)
*2 MAS9181CS (SO16)
NC
8
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
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PDIP 16
VDD 1
Vmax 2
SDA 3
SCL 4
A0 5
A1 6
A2 7
GND 8
MAS9181BN
16 DAC7
15 DAC6
14 DAC5
13 DAC4
12 DAC3
11 DAC2
10 DAC1
9 DAC0
SO16
MAS9181CS
VDD
Vmax
SDA
SCL
NC
A0
A1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
2
DA9181.006
13 October, 1999
Supply Voltage
Supply current
VDD
IDD
-0.5
-10
I C-bus line voltage
Input voltage
Output voltage
Maximum current on any
pin
total power dissipation
Operating ambient
temperature range
Storage temperature range
2
V(3),V(4)
Vin
Vo
Imax
Ptot
Tamb
Tstg
-0.5
-0.5
-0.5
Supply Voltage
Supply current
Total power dissipation
VDD
IDD
Ptot
No loads, Vmax=VDD=12V, All
data=00
OCT
No loads, Vmax=VDD=12V, All
data=00
OCT
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
Input voltage range
Input low voltage
Input high voltage
Input leakage current
Power-up reset
V
I
V
IL
V
IH
I
IL
Vin = 0V or VDD
-0.5
3.0
-1
3.5
+1
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40
5.9
V
V
VDD+0.5
VDD+0.5
10
500
-20
-65
+85
+150
o
o
mA
mW
C
C
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(conditions)
DA9181.006
13 October, 1999
Input voltage range
Input low voltage
Input high voltage
Input current low
Input current high
V
I
V
IL
V
IH
I
IL
I
IH
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
Pin 2 current
I
2
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
DAC output (pin 9 to 16)
Output voltage range
Output impedance
DAC output drive range
Output capacitive load
Vo
Io = +/- 100 A
Io = +/- 500 A
Zo
Io
Co
data = 7F
Upper side saturation voltage= 0.2v
Low side saturation voltage = 0.2v
-1
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
Output voltage low
V
OL
I
3
= 3.0 mA
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
Differential nonlinearity
Integral nonlinearity
Zero code error
1
1
1
DNL
INL
ZCE
PSRR
TCo
Io = 0 (without load)
Vmax = VDD-1.0
Io = 0 (without load)
Vmax = VDD-1.0
data = 00
-1.5
10
Power supply rejection
Zero code temperature coefficient
-200
Note 1: Guaranteed by design but not production tested
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C to 85
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C; VDD = 5V to 12V unless otherwise specified)
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0
VDD
1.0
V
V
V
3.0
-10
-15
1
A
A
7
10
A
0.1
0.2
30
VDD-0.1
VDD-0.2
V
V
1
2
mA
nF
0.4
V
-1
1
1.5
30
5
200
LSB
LSB
mV
mV/V
V/ C
o
4
DA9181.006
13 October, 1999
Bit Transfer on the I C-bus
SDA
SCL
Data line
stable
(data valid)
Change
of data
allowed
Complete Data Transfer
SDA
SCL
S
Start
condition
1-7
8
9
1-7
8
Address
R/W
Ack
Data
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The MAS9181 I C-bus interface is a receiver- only slave. Data is accepted from the I C - bus in the following
format.
S
0 1 0 0 A2 A1 A0 0
Address byte
A
I3 I2 I1 I0 SD SC SB
SA
Instruction byte
A
D7 D6 D5 D4 D3 D2 D1
D0
First data byte
A
P
2
2
S
P
A
Start condition
Stop condition
Acknowledgement
A2, A1, A0
I3, I2, I1, I0
SD, SC, SB, SA
D7, D6, D5, D4, D3, D2, D2, D1, D0
programmable address bits
instruction bits
sub-address bits
data bits
9
1-7
8
9
P
Ack
Data
Ack
Stop
condition
5
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