INTEGRATED CIRCUITS
DATA SHEET
OM6213
48
×
84 pixels matrix LCD driver
Product specification
File under Integrated Circuits, IC17
2001 Nov 07
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD driver
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
10
10.1
11
11.1
11.2
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
PIN FUNCTIONS
ROW 0 to ROW 47 row driver outputs
COL 0 to COL 83 column driver outputs
V
SS1
and V
SS2
: negative power supply rails
V
DD1
to V
DD3
: positive power supply rails
V
LCDOUT,
V
LCDIN
and V
LCDSENSE
: LCD power
supplies
V
OS0
to V
OS4
T1 to T7: test pads
SDIN: serial data line
SCLK: serial clock line
D/C: mode select
SCE: chip enable
OSC: oscillator
RES: reset
BLOCK DIAGRAM FUNCTIONS
Oscillator
Address counter (AC)
Display Data RAM (DDRAM)
Timing generator
Display address counter
LCD row and column drivers
V
LCD
generator
INITIALIZATION
ADDRESSING
Data structure
INSTRUCTIONS
Reset function
Function set
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.4
11.5
11.6
11.7
11.8
12
13
14
15
16
17
18
19
20
20.1
20.2
20.3
20.4
20.5
20.6
20.7
21
22
23
24
25
26
PD
V
H
Display Control
D, E
Set Y address of RAM
Set X address of RAM
Temperature Control
Bias value:
V
LCD
generator
OM6213
TEMPERATURE COMPENSATION
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
SERIAL INTERFACE
RESET
APPLICATION INFORMATION
MODULE MAKER PROGRAMMING
V
LCD
calibration
Charge pump multiplication factor
Bias system selected when BS[2:0] = 100
V
LCD
temperature coefficient selected when
TC[1:0] = 01 (TC1)
Seal bit
Module Maker parameter programming
Example of V
LCD
calibration flow
CHIP INFORMATION
BONDING PAD LOCATIONS
DEVICE PROTECTION DIAGRAM
TRAY INFORMATION
DEFINITIONS
LIFE SUPPORT APPLICATIONS
2001 Nov 07
2
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD driver
1
FEATURES
2
APPLICATIONS
OM6213
•
Single-chip LCD controller/driver
•
48 row, 84 column outputs
•
Display data RAM 48
×
84 bits
•
On-chip:
– Generation of LCD supply voltage (external supply
also possible)
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components (external
clock also possible).
•
External reset (RES) input pin
•
Serial interface maximum 4.0 Mbit/s
•
CMOS compatible inputs
•
Mux rate: 1 : 48
•
Logic supply voltage range V
DD1
to V
SS
: 2.5 to 3.3 V
•
Supply voltage range for high voltage part V
DD2
to V
SS
:
2.5 to 3.3 V
•
Display supply voltage range V
LCD
to V
SS
: 4.5 to 9.0 V
•
Low power consumption (typically 120
µA),
suitable for
battery operated systems
•
Temperature compensation of V
LCD
•
Temperature range: T
amb
=
−40
to +85
°C
•
5 Module Maker programmable parameters.
4
ORDERING INFORMATION
•
Telecommunications equipment.
3
GENERAL DESCRIPTION
The OM6213 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 48 rows and
84 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption. The
OM6213 interfaces to microcontrollers via a serial bus
interface.
PACKAGE
TYPE NUMBER
NAME
OM6213U
TRAY
chip with bumps in tray
DESCRIPTION
VERSION
−
2001 Nov 07
3
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD driver
5
BLOCK DIAGRAM
OM6213
handbook, full pagewidth
VDD1
VDD2
VDD3
COL 0 to COL 83
84
COLUMN DRIVERS
ROW 0 to ROW 47
48
ROW DRIVERS
VLCDIN
BIAS
VOLTAGE
GENERATOR
DATA LATCHES
SHIFT REGISTER
VLCDSENSE
VLCDOUT
VSS1
VSS2
VOS [4:0]
T1
T2
T3
T4
T5
T6
T7
VLCD
GENERATOR
DISPLAY DATA RAM
(DDRAM)
48
×
84 bits
RESET
RES
OSCILLATOR
OSC
TIMING
GENERATOR
ADDRESS COUNTER
DISPLAY
ADDRESS
COUNTER
DATA
REGISTER
OM6213
I/O BUFFER
MGT840
SDIN
SCLK
D/C
SCE
Fig.1 Block diagram.
2001 Nov 07
4
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD driver
6
PINNING
SYMBOL
V
OS4
V
OS3
V
OS2
V
OS1
V
OS0
V
DD1
V
DD3
V
DD2
SCLK
T7
SDIN
D/C
SCE
OSC
V
SS2
T4
T5
T6
V
SS1
7
7.1
PAD
3
4
5
6
7
13 to 18
19 to 22
23 to 30
31
32 to 35
36 to 39
40
41
42
43 to 50
51
52
53
54 to 61
DESCRIPTION
V
LCD
offset pad 0 input
V
LCD
offset pad 1 input
V
LCD
offset pad 2 input
V
LCD
offset pad 3 input
V
LCD
offset pad 4 input
supply voltage 1
supply voltage 3
supply voltage 2
serial clock input
test 7 alternative HV-gen
programming input
serial data input and HV-gen
programming input
data/command input
chip enable input (active
LOW)
oscillator input
ground 2
test 4 input
test 5 input
test 6 output
ground 1
7.5
RES
ROW 11 to
ROW 0
ROW 12 to
ROW 23
COL 0 to
COL 83
ROW 47 to
ROW 36
ROW 24 to
ROW 35
79
89 to 100
V
LCDOUT
V
LCDSENSE
71 to 77
78
OM6213
SYMBOL
T1
T2
T3
V
LCDIN
PAD
62
63
64
65 to 70
DESCRIPTION
test 1 output
test 2 output
test 3 output
V
LCD
supply voltage input and
HV-gen programming input
V
LCD
generator output
V
LCD
generator regulation
input
reset input (active LOW)
LCD row driver outputs
101 to 112 LCD row driver outputs
113 to 196 LCD column driver outputs
197 to 208 LCD row driver outputs
209 to 220 LCD row driver outputs
1, 8 to 12, dummy pads
81 to 88,
221 and
222
PIN FUNCTIONS
ROW 0 to ROW 47 row driver outputs
V
LCDOUT,
V
LCDIN
and V
LCDSENSE
: LCD power
supplies
These pads output the row signals.
7.2
COL 0 to COL 83 column driver outputs
These pads output the column signals.
7.3
V
SS1
and V
SS2
: negative power supply rails
If the internal V
LCD
generator is used, then all 3 pins must
be connected together. If not (the internal V
LCD
generator
is disabled and an external voltage is supplied at pin
V
LCDIN
), V
LCDOUT
must be left open-circuit and V
LCDSENSE
must be connected to V
LCDIN
. V
PR
must be set to logic 0 to
switch-off the charge pump if an external V
LCD
generator
is used. V
LCDIN
is also used for HV-gen programming.
7.6
V
OS0
to V
OS4
V
SS1
and V
SS2
must be connected together, jointly referred
to as V
SS
. When a pin has to be connected externally to
V
SS
, V
SS1
should be used.
7.4
V
DD1
to V
DD3
: positive power supply rails
V
DD1
provides the logic supply. V
DD2
and V
DD3
provide the
analog supply; jointly referred to as V
DD2
. V
DD2
and V
DD3
must be connected together.
Five input pins for on-glass V
LCD
offset. Each pin must be
connected to V
SS1
, which corresponds to logic 0, or to
V
DD1
, which corresponds to logic 1. All five pins define a
5-bit two’s complement number ranging from
−16
to +15
decimal (from 10000 to 01111). The default value, with all
pins connected to V
SS1
, is 0 decimal (00000). The register
is refreshed by each set bias system command or when
exiting the Power-down mode.
2001 Nov 07
5
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