Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed.
Electrical Characteristics
VCC = 4.75V to 5.5V for MIC705/MIC707, VCC = 4.5V to 5.5V for MIC706/MIC708, T
A
= -40°C to 85°C unless otherwise noted.
Parameter
Operating Voltage Range, VCC
Supply Current
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Pulse Width, t
RS
RESET Output Voltage
ISource = 800µA
ISink = 3.2mA
MIC70--C, ISink = 50µA, VCC = 1.4V
ISource = 800µA
ISink = 1.2mA
140
VCC - 1.5V
Conditions
MIC70--
MIC70--
MIC705, MIC707
MIC706, MIC708
4.50
4.25
4.65
4.4
40
200
280
Min
1.4
Typ
Max
5.5
60
4.75
4.5
Units
V
µA
V
mV
ms
V
0.4
0.3
V
0.4
1.6
2.25
sec
ns
V
0.8
-150
-50
50
µA
150
V
0.4
RESET Output Voltage
VCC - 1.5V
1.0
Watchdog Timeout Period, t
WD
WDI Minimum Input Pulse, t
WP
WDI Threshold Voltage
WDI Input Current
VIL = 0.4V, VIH = 80% of VCC
VIH, VCC = 5V
VIL, VCC = 5V
WDI = 0V
WDI = VCC
ISource = 800µA
ISink = 1.2mA
50
3.5
WDO Output Voltage
VCC - 1.5V
2
MIC705/6/7/8
µP
Supervisory Circuits
Electrical Characteristics
VCC = 4.75V to 5.5V for MIC705/MIC707, VCC = 4.5V to 5.5V for MIC706/MIC708, T
A
= -40°C to 85°C unless otherwise noted.
Parameter
MR Pull-Up Current
MR Pulse Width, t
MR
MR Input Threshold
MR to Reset Output Delay, t
MD
PFI Input Threshold
PFI Input Current
PFO Output Voltage
ISink = 3.2mA
VCC = 5V, ISource = 800µA
VCC = 5V
1.2
-25
VCC - 1.5V
1.25
0.01
VIL
VIH
Conditions
MR = 0V
Min
100
150
0.8
2.0
250
1.3
+25
0.4
nS
V
nA
V
Typ
250
Max
600
Units
µA
nS
V
3
MIC705/6/7/8
µP
Supervisory Circuits
Pin Functions
Pin No.
Pin Name
MR
MIC705
MIC706
1
MIC707
MIC708
1
Manual Reset Input forces RESET to assert when pulled below 0.8V.
An internal pull-up current of 250µA on this input forces it high when left
floating. This input can also be driven from TTL or CMOS logic.
Primary supply input, +5V.
IC ground pin, 0V reference.
Power fail input. Internally connected to the power fail comparator
which is referenced to 1.25V. The power fail output (PFO) remains
high if PFI is above 1.25V. PFI should be connected to GND or VOUT
if the power fail comparator is not used.
Power fail output. The power fail comparator is independent of all other
functions on this device.
Watchdog input. The WDI input monitors microprocessor activity, an
internal watchdog timer resets itself with each transition on the
watchdog input. If the WDI pin is held high or low for longer than the
watchdog timeout period, WDO is forced to active low. The watchdog
function can be disabled by floating the WDI pin.
No Connect
RESET is asserted if either VCC goes below the reset threshold or by a
low signal on the manual reset input (MR). RESET remains asserted
for one reset timeout period (200ms) after VCC exceeds the reset
threshold or after the manual reset pin transitions from low to high. The
watchdog timer will not assert RESET unless WDO is connected to
MR.
Output for the watchdog timer. The watchdog timer resets itself with
each transition on the watchdog input. If the WDI pin is held high or
low for longer than the watchdog timeout period, WDO is forced low.
WDO will also be forced low if VCC is below the reset threshold and
will remain low until VCC returns to a valid level.
RESET is the compliment of RESET and is asserted if either VCC goes
below the reset threshold or by a low signal on the manual reset input
(MR). RESET is suitable for microprocessors systems that use an
ARM技术
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