FLASH
AS29F040
512K x 8 FLASH
UNIFORM SECTOR 5.0V FLASH
MEMORY
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD-883
• SMD 5962-96692
PIN ASSIGNMENT
(Top View)
32-PIN Ceramic DIP (CW)
32-pin Flatpack (F)
32-pin Lead Formed Flatpack (DCG)
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE\
A17
A14
A13
A8
A9
A11
OE\
A10
CE\
DQ7
DQ6
DQ5
DQ4
DQ3
FEATURES
• Single 5.0V ±10% power supply operation
• Fastest access times: 55, 60, 70, 90, 120, & 150ns
• Low power consumption:
20 mA typical active read current
30 mA typical program/erase current
1
μA
typical standby current (standard access time to
active mode)
• Flexible sector architecture
Eight uniform 64 Kbyte each
Any combination of sectors can be erased
Supports full chip erase
• Sector protection
• Embedded Algorithms Erase & Program Algorithms
• Erase Suspend/Resume
• Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
• Compatible with JEDEC standards
Pinout and software compatible with single-power-
supply FLASH
• Data\ Polling and Toggle Bits
• 20-year data retention at 125°C
32-PAD Ceramic LCC (ECA)
A12
A15
A16
A18
VCC
WE\
A17
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4 3 2
32 31 30
5
29
1
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
A14
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
OPTIONS
OPTIONS
• Timing
55ns
60ns
70ns
90ns
120ns
150ns
MARKING
CW
F
DCG
ECA
IT
XT**
883C
Q
MARKING
-55
-60
-70
-90
-120
-150
• Package Type
Ceramic DIP (600 mil)
Flatpack
Lead Formed Flatpack
Leadless Chip Carrier
• Temperature Ranges
Industrial Temperature (-40°C to +85°C)
Military Temperature (-55°C to +125°C)
883C Processing (-55°C to +125°C)
QML Processing (-55°C to +125°C)
For more products and information
please visit our web site at
www.micross.com
AS29F040
Rev. 2.3 01/10
Micross Components reserves the right to change products or specifications without notice.
1
FLASH
AS29F040
GENERAL DESCRIPTION
The AS29F040 is a 4Mbit, 5.0 Volt-only FLASH memory
organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of
data are divided into eight sectors of 64 Kbytes each for
fl
ex-
ible erase capability. The 8 bits of data appear on DQ0-DQ7.
The device is designed to be programmed in-system with the
standard system 5.0 Volt V
CC
supply. A 12.0 volt V
PP
is not
required for write or erase operations. The device can also be
programmed in standard EPROM programmers.
This device is manufactured using 0.32
μm
process
technology. In addition, it has a second toggle bit, DQ2, and
offers the ability to program in the Erase Suspend mode.
It is available with access times of 55, 60, ^+^+6=70, 90,
120, and 150ns, allowing high-speed microprocessors to oper-
ate without wait states. To eliminate bus contention the device
has separate chip enable (CE\), write enable (WE\), and output
enable (OE\) controls.
The device requires only a single 5.0 volt power supply
for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The device is entirely command set compatible with the
JEDEC single-power-supply FLASH standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of
the device is similar to reading from other FLASH or EPROM
devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded Program
algorithm -- an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command
sequence. This invokes the Embedded Erase algorithm -- an
internal algorithm that automatically preprograms the array
(if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data\Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or accept
another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The device is fully erased when shipped from
the factory.
The hardware data protection measures include a low
V
CC
detector that automatically inhibits write operations
during power transitions. The hardware sector protection
feature disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
via programming equipment.
The erase suspect feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any sector that is not selected for erasure. True background
erase can thus be achieved.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode. The
device electrically erases all bits within a sector simultaneously
via Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
PIN CONFIGURATION
PIN
A0 - A18
DQ0 - DQ7
CE\
OE\
WE\
V
CC
V
SS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
+5V Single Power Supply
Device Ground
LOGIC SYMBOL
AS29F040
Rev. 2.3 01/10
Micross Components reserves the right to change products or specifications without notice.
2
FLASH
AS29F040
FUNCTIONAL BLOCK DIAGRAM
AS29F040
Rev. 2.3 01/10
Micross Components reserves the right to change products or specifications without notice.
3
FLASH
AS29F040
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the inter-
nal command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations table lists
the inputs and control levels required, and the resulting output.
The following subsections describe each of these operations in
further detail.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of memory),
the system must drive WE\ and CE\ to V
IL
, and OE\ to V
IH
.
An erase operation can erase one sector, multiple sectors,
or the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A “sector address” con-
sists of the address bits required to uniquely select a sector.
See the “Command Definitions” section for details on erasing
a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on DQ7 - DQ0. Standard read cycle
timings apply in this mode. Refer to the “Autoselect Mode”
and “Autoselect Command Sequence” sections for more infor-
mation.
I
CC2
in the DC Characteristics table represents the active
current specification for the write mode. The “AC
Char-
acteristics” section contains timing specification tables and
timing diagrams for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE\ and OE\ pins to V
IL
. CE\ is the power control and
selects the device. OE\ is the output control and gates array
data to the output pins. WE\ should remain at V
IH
.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains en-
abled for read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing wave-
forms. I
CC1
in the DC Characteristics table represents the active
current specification for reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on DQ7 - DQ0. Standard read cycle timings and I
CC
read
specifications apply. Refer to “Write Operation Status” for
more information, and to each AC Characteristics section for
timing diagrams.
Standby Mode
TABLE 1: DEVICE BUS OPERATIONS
OPERATION
Read
Write
CMOS Standby
TTL Standby
Output Disable
NOTES:
CE\
L
L
V
CC
± 0.5V
H
L
OE\
L
H
X
X
H
WE\
H
L
X
X
H
A0 - A20
A
IN
A
IN
X
X
X
DQ0 - DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
See the “Sector Protection/Unprotection” section for more information.
AS29F040
Rev. 2.3 01/10
Micross Components reserves the right to change products or specifications without notice.
4
FLASH
AS29F040
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE\ input.
The device enters the CMOS standby mode when the CE\
pin is held at V
CC
± 0.5V. (Note that this is a more restricted
voltage range than V
IH
.) The device enters the TTL standby
mode when CE\ is held at V
IH
. The device requires the standard
access time (t
CE
) before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation is
completed.
I
CC3
in the DC Characteristics table represents the standby
current specification.
shows the remaining address bits that are don’t care. When
all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on
DQ7 - DQ0
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register, as
shown in the Command Definitions table. This method does
not require V
ID
. See “Command Definitions” for details on
using the autoselect mode.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented us-
ing programming equipment. The procedure requires a high
voltage (V
ID
) on address pin A9 and the control pins. The
device is shipped with all sectors unprotected. It is possible
to determine whether a sector is protected or unprotected. See
“Autoselect Mode” for details.
Output Disable Mode
When the OE\ input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on DQ7 - DQ0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
requires V
ID
(11.5V to 12.5 V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in the Autoselect Codes (High
Voltage Method) table. In addition, when verifying
sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the
corresponding
Sector Address Tables. The Command
Definitions table
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
V
CC
power-up and power-down transitions, or from system
noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept
any write cycles. This protects data during V
CC
power-up and
TABLE 2: SECTOR ADDRESSES TABLE
SECTOR
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
AS29F040
Rev. 2.3 01/10
A18
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
ADDRESS RANGE
00000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 3FFFFh
40000h - 4FFFFh
50000h - 5FFFFh
60000h - 6FFFFh
70000h - 7FFFFh
Micross Components reserves the right to change products or specifications without notice.
NOTE:
All sectors are 64 Kbytes in size.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
