HD74LS221
Dual Monostable Multivibrators
REJ03D0458–0300
Rev.3.00
Jul.15.2005
This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which
can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the
transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free
triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity of
typically 1.2 V. A high immunity to V
CC
noise of typically 1.5 V is also provided by internal latching circuitry. Once
fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses may be of any duration
relative to the output pulse. Output rise and fall times are TTL compatible and independent of pulse length.
Typical triggering and clearing sequence are illustrated as a part of the switching characteristics waveforms. Pulse
width stability is achieved through internal compensation and is virtually independent of V
CC
and temperature.
In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free
operation is maintained over the full temperature and V
CC
range for more than six decades of timing capacitance (10 pF
to 10
µF)
and more than one decade of timing resistance (2 kΩ to 100 kΩ).
Throughout these ranges, pulse width is defined by the relationship: t
w (out)
= Cext
•
Rext
•
1n 2.
Features
•
Ordering Information
Part Name
HD74LS221P
HD74LS221RPEL
Package Type
DILP-16 pin
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
P
RP
Taping Abbreviation
(Quantity)
—
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.3.00, Jul.15.2005, page 1 of 8
HD74LS221
Pin Arrangement
1A
1B
1CLR
1Q
2Q
2 Cext
2 Rext/Cext
GND
1
2
3
4
5
Q
CLR
Q
Q
16
15
14
13
Q
CLR
V
CC
1 Rext/Cext
1 Cext
1Q
2Q
2CLR
2B
2A
12
11
10
9
6
7
8
(Top view)
Function Table
Inputs
Clear
A
L
X
X
H
X
X
H
L
H
↓
↑
L
Notes: H; high level, L; low level, X; irrelevant.
↓;
Transition from high to low level.
↑;
Transition from low to high level.
; one high-level pulse.
; one low-level pulse.
Outputs
B
X
X
L
↑
H
H
Q
L
L
L
Q
H
H
H
Block Diagram (1/2)
A
Q
Q
B
Clear
Q
Clear
Q
Rev.3.00, Jul.15.2005, page 2 of 8
HD74LS221
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
P
T
Tstg
Ratings
7
7
400
–65 to +150
Unit
V
V
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Rate of rise or fall of
input pulse
Input pulse width
Setup time
External timing resistance
External timing capacitance
Duty cycle
R
T
= 2 kΩ
R
T
= 100 kΩ
Schmitt input, B
Logic Input, A
A or B
Clear
Symbol
V
CC
I
OH
I
OL
T
opr
dV/dt
t
w (in)
t
w (clear)
t
su
R
ext
C
ext
Min
4.75
—
—
–20
1
1
40
40
15
1.4
0
—
—
Typ
5.00
—
—
25
—
—
—
—
—
—
—
—
—
Max
5.25
–400
8
75
—
—
—
—
—
100
1000
50
90
Unit
V
µA
mA
°C
V/s
V/µs
ns
ns
kΩ
µF
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Threshold
voltage
A
B
Symbol
V
T+
V
T–
V
T+
V
T
V
OH
V
OL
I
IH
Input current
A
B, Clear
I
IL
I
I
Short-circuit output
current
Supply current
Input clamp voltage
Note: * V
CC
= 5 V, Ta = 25°C
I
OS
I
CC
V
IK
–
Output voltage
min.
—
0.8
—
0.8
2.7
—
—
—
—
—
—
–20
—
—
—
typ.*
1.0
1.0
1.0
0.9
—
—
—
—
—
—
—
—
4.7
19
—
max.
2.0
—
2.0
—
—
0.4
0.5
20
–0.4
–0.8
0.1
–100
11
27
–1.5
Unit
V
V
V
V
V
V
µA
mA
mA
mA
mA
V
Condition
V
CC
= 4.75 V
V
CC
= 4.75 V
V
CC
= 4.75 V
V
CC
= 4.75 V
V
CC
= 4.75 V, I
OH
= –400
µA
I
OL
= 4 mA
V
CC
= 4.75 V
I
OL
= 8 mA
V
CC
= 5.25 V, V
I
= 2.7 V
V
CC
= 5.25 V, V
I
= 0.4 V
V
CC
= 5.25 V, V
I
= 7 V
V
CC
= 5.25 V
V
CC
= 5.25 V
Triggered
V
CC
= 4.75 V, I
IN
= –18 mA
Ouiescent
Rev.3.00, Jul.15.2005, page 3 of 8
HD74LS221
Switching Characteristics
(V
CC
= 5 V, Ta = 25°C)
Item
Symbol
t
PLH
Propagation
delay time
t
PHL
t
PHL
t
PLH
Inputs
A
B
A
B
Clear
Clear
Outputs
Q
Q
Q
Q
Q
Q
min.
—
—
—
—
—
—
70
20
t
w (out)
A or B
Q or
Q
600
6
670
6.7
750
7.5
ms
typ.
45
35
50
40
35
44
120
47
max.
70
55
80
65
55
65
150
70
ns
Unit
ns
ns
ns
ns
C
ext
= 80 pF,
R
ext
= 2 kΩ
C
ext
= 0 pF,
R
ext
= 2 kΩ
C
ext
= 100 pF,
R
ext
= 10 kΩ
C
ext
= 1
µF,
R
ext
= 10 kΩ
C
L
= 15 pF,
R
L
= 2 kΩ
C
ext
= 80 pF,
R
ext
= 2 kΩ
Condition
Output pulse
width
Caution in use
In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and
GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible.
Testing Method
Test Circuit
V
CC
A Input
P.G.
Z
out
= 50Ω
A
+
Cext
Cext
–
Rext
R
L
Q
C
L
Load circuit 1
Rext
/Cext
B Input
P.G.
Z
out
= 50Ω
CLR Input
P.G.
Z
out
= 50Ω
B
CLR
Q
Same as Load Circuit 1.
Notes:
1. C
L
includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Rev.3.00, Jul.15.2005, page 4 of 8
HD74LS221
Waveforms 1
Trigger from B, then clear (A input is low).
t
TLH
90%
1.3V
≥
60ns
3V
CLR
t
PLH
Q
t
PHL
Q
1.3V
t
PLH
V
OH
1.3V
1.3V
V
OL
1.3V
0V
t
PHL
3V
1.3V
0V
t
w (in)
90%
1.3V
t
THL
3V
B Input
10%
10%
0V
Note:
Input pulse: t
TLH
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz
Waveforms 2
Trigger from A, then clear (B input is high).
t
THL
t
w (in)
A
90%
1.3V
90%
1.3V
0V
3V
CLR
1.3V
0V
t
PLH
Q
1.3V
t
PLH
V
OH
Q
t
PHL
1.3V
1.3V
V
OL
t
PHL
V
OH
1.3V
V
OL
t
TLH
3V
10%
≥
60ns
10%
Note:
Input pulse: t
TLH
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz
Rev.3.00, Jul.15.2005, page 5 of 8
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