CAT93C66
4-Kb Microwire Serial CMOS EEPROM
FEATURES
High speed operation: 2MHz
1.8V to 5.5V supply voltage range
Selectable x8 or x16 memory organization
Sequential read
Software write protection
Power-up inadvertant write protection
Low power CMOS technology
1,000,000 Program/erase cycles
100 year data retention
Industrial and Extended temperature ranges
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
8-pad TDFN packages
For Ordering Information details, see page 15.
DESCRIPTION
The CAT93C66 is a 4-Kb CMOS Serial EEPROM
device which is organized as either 256 registers of 16
bits (ORG pin at V
CC
) or 512 registers of 8 bits (ORG
pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C66
features sequential read and self-timed internal write
with auto-clear. On-chip Power-On Reset circuitry
protects the internal logic against powering up in the
wrong state.
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TSSOP (Y)
TDFN (VP2, ZD4)*
CS
SK
DI
DO
1
2
3
4
8 V
CC
7 NC
6 ORG
5 GND
NC
V
CC
CS
SK
FUNCTIONAL SYMBOL
V
CC
SOIC (W)*
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
ORG
CS
SK
DI
CAT93C66
DO
* TDFN 3x3mm (ZD4) and SOIC (W) rotated pin-out packages are
available only for Die Rev E (not recommended for new designs)
GND
PIN FUNCTION
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1089 Rev. R
CAT93C66
Absolute Maximum Ratings
(1)
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
Reliability Characteristics
(3)
Symbol
NEND
(4)
TDR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
Ratings
-65 to +150
-0.5 to +6.5
Units
°C
V
D.C. OPERATING CHARACTERISTICS (New Product, Die Rev. G)
V
CC
= +1.8V to +5.5V, T
A
=-40°C to +125°C unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, V
CC
= 5V, 25°C
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16 Mode)
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz, V
CC
= 5.0V
f
SK
= 1MHz, V
CC
= 5.0V
V
IN
= GND or V
CC
,
CS = GND ORG = GND
V
IN
= GND or V
CC
,
CS = GND ORG = Float
or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CS = GND
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V,
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V,
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V,
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V,
I
OH
= -100µA
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Min
Max
1
500
2
4
1
2
1
2
1
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
-0.1
2
0
V
CC
x 0.7
2.4
0.2
V
CC
- 0.2
V
V
Doc. No. MD-1089 Rev. R
Characteristics subject to change without notice
2
© Catalyst Semiconductor, Inc.
CAT93C66
D.C. OPERATING CHARACTERISTICS (Mature Product, Die Rev. E – NOT RECOMMENDED FOR NEW
DESIGNS)
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16 Mode)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz, V
CC
= 5.0V
f
SK
= 1MHz, V
CC
= 5.0V
V
IN
= GND or V
CC
, CS = GND
ORG = GND
V
IN
= GND or V
CC
, CS = GND
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
, CS = GND
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V, I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V, I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V, I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V, I
OH
= -100µA
V
CC
- 0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
Min
Max
3
500
10
10
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
PIN CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0V
V
IN
= 0V
Min
Typ
Max
5
5
Units
pF
pF
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1089 Rev. R
CAT93C66
A.C. CHARACTERISTICS
(1)
(New Product, Die Rev. G)
V
CC
= +1.8V to +5.5V, T
A
= -40°C to +125°C, unless otherwise specified.
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(2)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
Min
50
0
100
100
0.25
0.25
100
5
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
A.C. CHARACTERISTICS
(1)
(Mature Product, Die Rev E – NOT RECOMMENDED FOR NEW DESIGN)
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(2)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Notes
:
(1)
(2)
Test conditions according to “A.C. Test Conditions” table.
These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
V
CC
= 1.8V - 5.5V
Min
200
0
400
400
1
1
400
10
1
1
1
1
DC
250
Max
V
CC
= 2.5V - 5.5V
Min
100
0
200
200
0.5
0.5
200
10
0.5
0.5
0.5
0.5
DC
500
Max
V
CC
= 4.5V - 5.5V
Min
50
0
100
100
0.25
0.25
100
10
0.25
0.25
0.25
0.25
DC
1000
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
Doc. No. MD-1089 Rev. R
Characteristics subject to change without notice
4
© Catalyst Semiconductor, Inc.
CAT93C66
POWER-UP TIMING
(1) (2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
Notes
:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
A.C. Test Conditions
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50 ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
Current Source I
OLmax
/I
OHmax
; CL=100pF
DEVICE OPERATION
The CAT93C66 is a 4096-bit nonvolatile memory
intended for use with industry standard micropro–
cessors. The CAT93C66 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 11-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 12-bit instructions control the reading, writing and
erase operations of the device. The CAT93C66 operates
on a single power supply and will generate on chip, the
high voltage required during any write operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
1
Address
Opcode
10
11
01
00
00
00
00
x8
A8-A0
A8-A0
A8-A0
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
x16
A7-A0
A7-A0
A7-A0
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
x8
Data
x16
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 8-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The instruction format is shown in
Instruction Set table.
D7-D0
D15-D0
D7-D0
D15-D0
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1089 Rev. R
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