to the device. This is a stress rating only, and the functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%, Unless Otherwise Specified
DC Operating Conditions
Symbol
V
CC
I
CC
I
CC
I
SB
(2)
I
SB
(2)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
V
HYS
(3)
Parameter
Power Supply Voltage
V
CC
Supply Current
V
CC
Supply Current
Standby Current 0 to 70°C
Standby Current -40 to 85°C
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Input Hysteresis
Min
4.5
Typ
(1)
Max
5.5
100
300
25
60
10
10
Units
V
µA
µA
µA
µA
µA
µA
V
V
V
V
V
I
OL
= 3mA
I
OL
= 6mA
Test Conditions
5.0
60
180
8
16
SCL @ 100KHz, Read or Write
SCL CMOS Levels, All Other Inputs = V
SS
or V
CC
- 0.3V
SCL @ 400KHz, Read or Write
SCL CMOS Levels, All Other Inputs = V
SS
or V
CC
- 0.3V
SCL = SDA = V
CC
, All Other Inputs = V
SS
or V
CC
SCL = SDA = V
CC
, All Other Inputs = V
SS
or V
CC
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
-1.0
V
CC
x 0.7
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.6
V
CC
x .05
(1) Typical values are measured at 25°C, 5.0V
(2) Must perform a stop command prior to measurement.
(3) This paramter is periodically sampled and not 100% tested.
Power-Up Timing
(4)
Symbol
Parameter
Power Up to Read Operation
Power Up to Write Operation
Endurance and Data Retention
Parameter
Endurance
Data Retention
Max
1
1
Units
µs
µs
Min
10 Billion
10
Max
Units
R/W Cycles
Years
t
PUR (4)
t
PUW (4)
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified oper-
ation can be initiated. These parameters are periodically sampled and not 100% tested.
AC Conditions of Test
AC Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Test
V
CC
x 0.1 to V x 0.9
CC
10ns
V
CC
x 0.5
Equivalent AC
Load Circuit
Output
5.5V
1800 Ω
100pF
Capacitance
Symbol
C
I/O (3)
C
IN (3)
T
A
= 25°C, f = 1.0MHz, V
CC
= 5V
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP)
Max
8
6
Units
pF
pF
V
I/O
= 0V
V
IN
= 0V
Conditions
(3) This paramter is periodically sampled and not 100% tested.
2
Pin Descriptions
SCL — Serial Clock
When high, the SCL clocks data into and out of the FM24164. It
is an input only. This input is built with a Schmitt trigger to provide
increased noise immunity.
Bus Protocol
The FM24164 employs a bi-directional two wire bus protocol
requiring a minimum of processor I/O pins. Figure 1 shows a
typical system configuration connecting a microcontroller with
eight FM24164 devices.
By convention, any device sending data onto the bus is the
transmitter, while the device that is getting the data is the receiver.
SDA — Serial Data Address
The device controlling the bus is the master and provides the clock
This bi-directional pin is used to transfer addresses to the
signal for all operations. Devices being controlled are the slaves.
FM24164 and data to or from the FM24164. It is an open drain
The FM24164 is always a slave device.
output and intended to be wire-ORed with all other devices on the
Transitions or states on the SDA and SCL lines denote one of
serial bus using an external pull-up resistor. The input circuitry on four conditions: a
start, stop, data bit,
or
acknowledge.
Figure 2
this pin is built with a Schmitt trigger to reduce noise sensitivity.
shows the signaling for these conditions, while the following four
The output section incorporates slope control for the falling edges. sections describe their function.
Figure 3 shows the detailed timing specifications for the bus.
WP — Write Protect
Note that all SCL specifications and the
start
and
stop
specifications
If tied to V
CC
, write operations into the upper half of the
apply to both read and write operations. They are shown on one or
memory (page select A
2
set to 1 in the slave address) will be
the other for clarity. Also, the write timing specifications apply to all
disabled. Read and write operations to the lower portion of
transmissions to the FM24164, including the slave and word
memory will proceed normally. If the write protection feature is not address, as well as write data sent to the FM24164 from the bus
desired, this pin must be tied to V
SS
.
master.
Figure 1. Typical System Configuration
R
SCL
R
R
MIN
= 1.8K
R
MAX
= t
R
/ C
BUS
Bus
Master
SDA
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
FM24164
S
2
S
1
S
0
FM24164
S
2
S
1
S
0
FM24164
S
2
S
1
S
0
FM24164
(Up to 8 Total)
S
2
S
1
S
0
V
CC
V
SS
Slave Address
Device Select
S2, S1, S0
(Bit Nos. 6, 5, 4)
Figure 2. Data Transfer Protocol
SCL
SDA
{
0
0
0
0
0
1
0
1
0
1
1
1
7
6
0
Stop
(Master)
Start
(Master)
Data Bit
(Transmitter)
Data Bit
(Transmitter)
Data Bit
(Transmitter)
Acknowledge
(Receiver)
3
Figure 3. Bus Timing
Read
t
RISE
t
FALL
t
HIGH
1/f
SCL
t
LOW
t
SP
t
SP
SCL
t
SU:STA
t
BUF
VALID
t
AA
VALID
t
DH
t
SU:DAT
t
HD:DAT
SDA
Start
Stop
Start
Data Bit 7
From FM24164
Data Bit 6
From FM24164
Data Bits 5-0
From FM24164
Acknowledge
To FM24164
Write
SCL
t
HD:STA
t
SU:STO
t
SU:DAT
VALID
VALID
t
HD:DAT
t
AA
t
DH
SDA
Start
Stop
Start
Data/Address Bit 7
To FM24164
Data/Address Bit 6
To FM24164
Data/Address Bits 5-0
To FM24164
Acknowledge
From FM24164
Notes:
All start and stop timings apply to both read and write cycles identically.
Clock specifications are the same for both read and write.
Write timing specifications apply to slave address, word address, and write data.
These timing diagrams provide representative timing relationships of the signals. They are not intended to provide functional relationships between the signals. These are provided in
Figures 5 through 9.
Read and Write Cycle AC Parameters
Symbol
f
SCL
t
SP
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
RISE(3)
t
FALL(3)
t
SU:STO
t
DH
t
OF
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time (From SCL @ V
IL
)
Output Fall Time (V
IH
Min to V
IL
Max)
4.0
0
4.7
4.0
4.7
4.0
4.7
0
250
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%, Unless Otherwise Specified
Parameter
Standard Mode
Min
0
Fast Mode
Min
0
Max
100
50
3
Max
400
50
0.9
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
1.3
0.6
1.3
0.6
0.6
0
100
1000
300
20+0.1C
b(5)
20+0.1C
b(5)
0.6
0
250
20+0.1C
b(3)
250
300
300
ns
ns
µs
ns
ns
(3) This paramter is periodically sampled and not 100% tested.
(5) C
b
= Total Capacitance of One Bus Line in pF
4
Bit 7 is a binary 1.
Bits 4, 5, and 6 are the device select bits. A system can have up
A
start
condition is indicated to the FM24164 when there is a
to eight FM24164 devices on a single I
2
C bus. The eight
high to low transition of SDA while SCL is high. All commands to
addresses are defined by the state of the S
0
, /S
1
, and S
2
inputs
the FM24164 must be preceded by a
start.
In addition, a
start
(pins 1, 2, and 3). A device is selected when the device select
condition occurring at any point within an operation will abort that
bits (4 and 6) of the slave address match the state of the input
operation and ready the FM24164 to start a new one.
pins 1 and 3, and bit 5 of the slave address matches the inverse
of pin 2.
Stop Condition
s
Bits 1 through 3 are the page select bits. They select which 256-
A
stop
condition is indicated to the FM24164 when there is a
byte block of memory will be accessed by this operation.
low to high transition of SDA while SCL is high. All operations to the
FM24164 should end with a
stop.
In addition, any operation will be
s
Bit 0 is the read/write bit. If set to a 1, a read operation is being
performed by the master; otherwise, a write is intended.
aborted at any point when this condition occurs.
s
s
Start Condition
Word Address
After a slave device
acknowledges
the slave address on a write
operation, the master will place the word address on the bus. This
byte, in addition to the three page select bits from the slave address
byte, forms the address of the byte within the memory that is to be
written. This 11-bit value is latched in the internal address latch.
There is no word address specified during a read operation,
although the upper three bits of the internal latch are set to the
Acknowledge
page select values in the slave address.
Acknowledge transfers take place on the ninth clock cycle
During the transmission of each data byte and before the
after each eight-bit address or data transfer. During this clock
cycle, the transmitter will release the SDA bus to allow the receiver acknowledge cycle, the address in the internal latch is incremented
to allow the following byte to be accessed immediately. When the
to drive the bus low to acknowledge receipt of the byte.
If the receiver does not acknowledge any byte, the operation is last byte in the memory is accessed (at address hex 7FF), the
address is reset to 0. There is no alignment requirement for the
aborted.
first byte of a block cycle — any address may be specified. There is
also no limit to the number of bytes that may be accessed in a
Device Operation
single read or write operation.
Low Voltage Protection
Data Transfer
When powering up, the FM24164 will automatically perform
After all address bytes have been transmitted, data will be
an internal reset and await a
start
signal from the bus master. The
transferred between the FM24164 and the bus master. In the case
bus master should wait T
PUR
(or T
PUW
) after V
CC
reaches 4.5V
of a read, the FM24164 will place each of the eight bits on the bus
before issuing the
start
for the first read or write access.
Additionally, whenever V
CC
falls below 3.5V (typical), the part goes and then wait for an acknowledge from the bus master before
performing a read on the subsequent address. For a write
into its low voltage protection mode. In this mode, all accesses to
the part are inhibited and the part performs an internal reset. If an operation, the FM24164 will accept eight bits from the bus master
and then drive the acknowledge on the bus.
access was in progress when the power supply fails, it will be
All data and address bytes are transmitted most significant bit
automatically aborted by the FM24164. When power rises back
above 4.5V, a
start
signal must be issued by the bus master to
(bit 7) first.
initiate an access.
After the acknowledge of a data byte transfer, the bus master
may either begin another read or write on the subsequent byte,
Slave Address
issue a
stop
command to terminate the block operation, or issue a
start
command to terminate the current operation and start a new
Following a
start,
the FM24164 will expect a slave address
one.
byte to appear on the bus (see Figure 4).
Figure 4. Slave Address
Device Select
Bits
Page
Select
Data/Address Transfers
Data/address transfers take place during the period when SCL
is high. Except under the two conditions described above, the state
of the SDA line may not change while SCL is high. Address transfers
are always sent to the FM24164, while data transfers may either be
sent to the FM24164 (for a write) or to the bus master (for a
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