128Mx72 bit
s
Registered DDR SDRAM DIMM
HYMD512G726A(L)8-M/K/H/L
DESCRIPTION
Preliminary
Hynix HYMD512G726A(L)8-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726A(L)8-
M/K/H/L series consists of eighteen 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy sub-
strate. Hynix HYMD512G726A(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form fac-
tor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD512G726A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD512G726A(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function
is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-
tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
•
•
•
•
•
•
1GB (128M x 72) Registered DDR DIMM based on
64Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Error Check Correction (ECC) Capability
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
•
•
•
•
•
•
•
Fully differential clock operations (CK & /CK) with
125MHz/133MHz
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD512G726(L)8-M
HYMD512G726(L)8-K
HYMD512G726(L)8-H
HYMD512G726(L)8-L
V
DD
=2.5V
V
DDQ
=2.5V
Power Supply
Clock Frequency
133MHz (*DDR266 2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
125MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Registered DIMM
5.25 x 1.7 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Jan. 2003
1
HYMD512G726A(L)8-M/K/H/L
PIN DESCRIPTION
Pin
CK0, /CK0
CS0, CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A12
BA0, BA1
DQ0~DQ64
CB0~CB7
DQS0~DQS7
DM0~8
VDD
/RESET
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Reset Enable
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
WP
VDDID
DU
NC
FETEN
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
Write Protect Flag
VDD Identification Flag
Do not Use
No Connection
FET Enable
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
/RESET
VSS
DQ8
DQ9
DQS1
VDDQ
DU
DU
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
53
54
55
56
57
58
59
60
61
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Name
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
DU
DU
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
WP
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Name
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
CB7
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
145
146
147
148
149
150
151
152
153
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
CB6
VDDQ
CB7
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC, FETEN*
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
*
These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.1/Jan. 2003
2
HYMD512G726A(L)8-M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
/RCS1
/RCS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
.
DQS4
DM4
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
.
/CS
DQS
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D13
DQS5
DM5
/CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D10
D5
D14
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D2
D11
D6
D15
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D3
D12
D7
D16
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
Serial PD
SCL
WP
A0
SA0
VDDSPD
VDDQ
VDD
VREF
VSS
A1
SA1
A2
SA2
SDA
D17
/CS0
/CS1
BA0-BA1
A0-A12
/RAS
/CAS
CKE0
CKE1
/WE
PCK
/PCK
R
E
G
/RCS0 -->/CS0 : SDRAMs D0-D8
/RCS1-->/CS1 : SDRAMs D9 - D17
RBA0-RBA1--> : BA0-BA1:SDRAMs D0-D17
RA0 -R A12 -->A0 - A12 : SDRAMs D0 - D17
/RRAS --> /RAS : SDRAMs D0 - D17
/RCAS --> /CAS : SDRAMs D0 - D17
RCKE0 --> CKE : SDRAMs D0 - D8
RCKE1 --> CKE : SDRAMs D9-D17
/RWE --> /WE : SDRAMs D0 - D17
/RESET
CK0, /CK0 --------- PLL*
* Wire per clock loading table/wiring diagrams
VDDID
.
= =
.
.
...
=
.
..
.
=
.
SPD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
Strap:see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ/DQS resistors should be 18 Ohms.
4. VDDID strap connections(for memory device VDD, VDDQ);
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD=VDDQ
5. /RS0 and /RS1 alternate btw the back and front sides of the DIMM
6. Address and control resistors should be 22 Ohms
Rev. 0.1/Jan. 2003
3
HYMD512G726A(L)8-M/K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
18
260
/
10
Rating
o
o
Unit
C
C
V
V
V
mA
W
o
C
/
Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
Symbol
Min
2.3
2.3
V
REF
+ 0.15
-0.3
V
REF
- 0.04
0.49*VDDQ
Typ.
2.5
2.5
-
-
V
REF
0.5*VDDQ
Max
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
0.51*VDDQ
Unit
V
V
V
V
V
V
3
2
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+ 0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1/Jan. 2003
4
HYMD512G726A(L)8-M/K/H/L
AC OPERATING TEST CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (V
IH
, min)
AC Input Low Level Voltage (V
IL
, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (R
T
)
Series Resistor (R
S
)
Output Load Capacitance for Access Time Measurement (C
L
)
Value
V
DDQ
x 0.5
V
DDQ
x 0.5
V
REF
+ 0.31
V
REF
- 0.31
V
REF
V
TT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
Ω
Ω
pF
Rev. 0.1/Jan. 2003
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
