AVPro® 5303B
Universal 3-Input A/V Switch Interface
DATA SHEET
DECEMBER 2005
DESCRIPTION
VCC
VCC
The AVPro
®
5303B device is a universal three input A/V
switch interface IC designed for TV and general-purpose
A/V applications. The device provides interfaces for
three full sets of TV SCART input signals
(Red, Green,
Blue, CVBS, R, L, Fast Blanking, and TV Function) and
also supports SCART
SVHS video mode. In addition, the
VCC
VDD
Dev_Addr
Func1
Func2
Func3
FB1
FB2
FB3
Green
or
Y
or
CVBS
0V/6V/12V
5303B can be configured to support general-purpose
A/V interface (YPrPb, SVHS, and CVBS) for TVs, DVD
recorders, digital set-top boxes, and PVRs. Video and
audio gains are programmable. All switching and
function settings are controlled via I
2
C.
Mux
Func_out
Mux
FB_out
Gain
FEATURES
Three Input A/V Interface
•
•
•
•
•
3:1 video and audio mux
Programmable gain video drivers
0/6 dB audio drivers
TV SCART Interface
-
RGB+FB, SVHS and CVBS video modes
-
12V TV Function pins mux
General Purpose A/V Interface
-
YPrPb, SVHS and CVBS video modes
Gn1
Gn2
Gn3
Bl1
Bl2
Bl3
Rd1
Rd2
Rd3
Mux
Gn_out
Blue
or
Pb
Mux
Bl_out
Red
or
Pr
or
C
Mux
Rd_out
Gain
I
2
C Control
Power Down Mode
Configurable Device Address
•
•
•
•
Picture-in-Picture Application
Expandable Multi-function Inputs (up to 6 channels)
+5V, +12V
48-QFN
CVBS
or
Y
CVBS1
CVBS2
CVBS3
R1
R2
R3
L1
L2
L3
SCLK
SDATA
Pdwn
Mux
CVBS_out
0/6dB
Mux
R_out
Power Supply
Package
Mux
L_out
Vref
Support
Circuits
APPLICATIONS
TV 3-SCART Interface
TV A/V Interface (YPrPb/SVHS/CVBS)
DVD Recorder A/V Interface
Digital Set-Top Box A/V Interface
PVR A/V Interface
Serial
Port
Rbias
Tgen
GND
GND
Page: 1 of 16
GND
GND
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.0
AVPro® 5303B
Universal 3-Input A/V Switch Interface
DATA SHEET
Functional Description
The 5303B is an analog A/V interface IC designed for
TV and general-purpose A/V applications. The device
accepts up to three sets of SCART input signals (Red,
Green, Blue, CVBS, R, L, Fast Blanking, and TV
Function). By way of 3:1 mux, SCART 1, 2, or 3 signals
can be selected at the device’s output pins. The 5303B
supports four SCART video modes: RGB/CVBS, RGB-
only, CVBS-only and SVHS. The RGB and CVBS video
driver gains are programmable from 2 to 1.4 in 0.2
steps, and the R/L audio driver gain can be 0dB or 6dB.
The R/L audio drivers can accept signals from 0.5Vrms
to 2Vrms.
For general-purpose A/V applications, video switches
and drivers can be configured to support component
video (YPrPb), S-Video (SVHS), and composite video
(CVBS) signals.
A/V Input Source Selection
The device accepts up to three sets of A/V input
signals. Bits 0 & 1 of Register 0 determine which of the
sets will be present at the device’s output pins.
Video Mode Selection
The device supports four video modes for TV SCART
applications: RGB/CVBS, RGB-only, CVBS-only, and
SVHS. Bits 2, 3, & 4 set the active video mode.
RGB/CVBS video mode is a default mode. For general-
purpose A/V applications, the device supports
YPrPb/CVBS and CVBS/SVHS video modes.
RGB Gain
The gain of the RGB outputs can be adjusted to one of
four different levels. Bits 0 & 1 Register 1 set the gain
of the RGB output amplifiers according to the following
table:
Bit 1
0
0
1
1
Bit 0
0
1
0
1
RGB Amplifier Gain
Gain = 2 V/V
Gain = 1.8 V/V
Gain = 1.6 V/V
Gain = 1.4 V/V
All switching and programmable functions of the
device are controlled through a standard I
2
C serial
interface
DC Restore for RGB, Y, and CVBS:
The device will
generate a DC restore level on each video output based
on timing referenced to a horizontal sync pulse. When
the sync pulse is detected, the DC restore circuit will act
to position the blank level to 1.2V at the respective RGB,
Y, or CVBS output pin(s).
CVBS Gain
The gain of the CVBS output can be adjusted to one of
four different levels. Bits 2 & 3 Register 1 set the gain
of the CVBS output amplifier according to the following
table:
Bit 3
0
0
1
1
Bit 2
0
1
0
1
CVBS Amplifier Gain
Gain = 2 V/V
Gain = 1.8 V/V
Gain = 1.6 V/V
Gain = 1.4 V/V
DC Restore for SVHS and YPrPb:
In the SVHS
mode, the CVBS pin is used as Luma input and the
Red pin is used as Chroma input. The DC restore
function for Luma signal is equivalent to CVBS signal.
The DC restore circuit will position the output blank level
to 1.2V at the respective Luma output pin. For the
Chroma input, the on-chip clamp circuit will be used to
position the output mid-scale DC level to 1.8V. In the
YPrPb mode, the mid-scale DC level for Pr and Pb
outputs will also be at 1.8V.
Audio Gain
The gain of the R/L audio amplifiers can be set to either
0dB or 6dB. Bit 4 of Register 1 sets the gain of the
amplifiers according to the following table:
Bit 4
0
1
R/L Amplifier Gain
Gain = 0 dB
Gain = 6 dB
Page: 2 of 16
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.0
AVPro® 5303B
Universal 3-Input A/V Switch Interface
DATA SHEET
TV Function Input
The TV Function feature generally supports three-level
logic signal required for SCART TV Function Switching:
Input Voltage
0-2V
4.5-7V
9.5-12V
TV Function Switching Mode
Broadcast TV
16:9 Peritelevision Reproduction
Normal Peritelevision Reproduction
Serial Port Definition
Internal functions of the device are monitored and
controlled by a standard inter-IC (I
2
C)bus with data
being transferred MSB first on the rising edge of the
clock. The serial port operates in a slave mode only
and can be written to or read from. The device uses
7-bit addressing, and does not support 10-bit
addressing mode. The write register data is sent
sequentially, such that if register 1 is to be
programmed, then registers 0 and 1 need to be sent.
If only register 0 needs to be programmed, then only
registers 0 data needs to be sent. It will support
standard and fast bus speed. The default address
of the device is 1001000x (1001000 for Write and
10010001 for Read).
The 5303B includes a read register in which the upper
four bits identify the specific chip within the AVPro
®
family. This allows a single application platform and
software to work with a wide variety of AVPro
®
chips.
The ID code for the 5303B is 0010.
In the AVPro® 5303B device, the TV Function
feature works in pass through mode only.
The three
inputs, Func1, Func2 and Func3 support the pass
through mode of the TV Function feature
. A 100kΩ
load is recommended for typical operation at the
Func_out pin.
Fast Blanking (FB) Input
The FB1, FB2 and FB3 inputs support two-level logic
signal required for SCART Fast Blanking:
Logic
0
1
Input Voltage
0-0.4V
1-3V
Fast Blanking Mode
CVBS Active
RGB Active
Data Transfers
A data transfer starts when the
SDATA
pin is driven
from HIGH to LOW by the bus master while the
SCLK
pin is HIGH. On the following eight clock cycles, the
device receives the data on the
SDATA
pin and
decodes that data to determine if a valid address has
been received. The first seven bits of information are
the address with the eighth bit indicating whether the
cycle is a read (bit is HIGH) or a write (bit is LOW). If
the address is valid for this device, on the falling
SCLK
edge of the eighth bit of data, the device will drive the
SDATA
pin low and hold it LOW until the next rising
edge of the
SCLK
pin to acknowledge the address
transfer. The device will continue to transmit or receive
data until the bus master has issued a stop by driving
the
SDATA
pin from LOW to HIGH while the
SCLK
pin
is held HIGH
Write Operation:
When the read/write bit (LSB) is
LOW and a valid address is decoded, the device will
receive data from the
SDATA
pin. The device will
continue to latch data into the registers until a stop
condition is detected. The device generates an
acknowledge after each byte of data written.
Read Operation:
When the read/write bit (LSB) is
HIGH and a valid address is decoded, the device will
transmit the data from the internal register on the
following eight
SCLK
cycles. Following the transfer of
the register data and the acknowledge from the master,
the device will release the data bus.
Reset:
At power-up the serial port defaults to the states
indicated in boldface type. The device also responds to
the system level reset that is transmitted through the
serial port. When the master sends the address
00000000 followed by the data 00000110, the device
resets to the default condition.
Rev 1.0
Following a 3:1 input mux stage is a unity-gain FB
video driver. The FB video driver is designed to
match the video drivers of RGB in bandwidth and
time delay and can support a minimum load of
300Ω.
Chip Power Down
The whole chip (except negligible on-chip biasing
circuit) can be powered down by setting Pdwn pin to
high (5V).
Configurable Device Address
Dev_Addr pin sets the address of the 5303B device.
There are two possible device addresses that the
5303B can have:
Device Address
1001000x
1010000x
Description
Dev_Addr pin left OPEN (Default)
Dev_Addr pin connected to GND
In the case of picture-in-picture or 6-channel inputs
application, a second device is required to have a
different address from the first or original device.
This can be done by connecting the Dev_Addr pin of
the second device to GND while leaving the
Dev_Addr pin of the first device OPEN or
unconnected.
Page: 3 of 16
©
2005 TERIDIAN Semiconductor Corporation
AVPro® 5303B
Universal 3-Input A/V Switch Interface
DATA SHEET
SERIAL PORT REGISTER TABLES
Read register
Device Address = 10010001 (10100001 when Dev_Addr = 0)
Function
Not Used
Device ID Code
Bits
xxxx0000
0010xxxx
Description
Not Used
This code identifies the device type as the 5303B.
Write Registers:
Device Address = 10010000 (10100000 when Dev_Addr = 0).
Bold
indicates default setting.
Register 0: Signal Source Selection
Register 0:
Video Mode
BLUE Chroma/Pr/Pb enable
RED Chroma/Pr/Pb enable
FB_OUT set to 0V
GN_OUT set to 0V
Audio/FUNC Source Selection
Bits
xxxxxxx0
xxxxxxx1
xxxxxx0x
xxxxxx1x
xxxxx0xx
xxxxx1xx
xxxx0xxx
xxxx1xxx
Bits
00xxxxxx
01xxxxxx
10xxxxxx
11xxxxxx
Description
Blue input set for Chroma/Pr/Pb
Blue input set for Y or Blue(DC Restore)
Red input set for Chroma/Pr/Pb
Red input set for Y or Red(DC Restore)
FB_OUT for normal operation
FB_OUT SET TO 0V
GN_OUT for normal operation
GN_OUT SET TO 0V
ROUT
R1
R2
R3
Not Used
LOUT
L1
L2
L3
Not Used
FUNC_OUT
FUNC1
FUNC2
FUNC3
Not Used
Register 1: Audio/Video Gain Control
Function
RBG Gain
Bits
xxxxxx00
xxxxxx01
xxxxxx10
xxxxxx11
Function
CVBS Gain
Bits
xxxx00xx
Xxxx01xx
Xxxx10xx
Xxxx11xx
Function
Audio Gain
Bits
xxx0xxxx
xxx1xxxx
Description
2
1.8
1.6
1.4
Description
2
1.8
1.6
1.4
Description
0 dB
6 dB
Page: 4 of 16
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.0
AVPro® 5303B
Universal 3-Input A/V Switch Interface
DATA SHEET
Register 2: XXXX XXXX. User must write to register 2 (contents written are a don’t care) prior to writing to
register 3.
Register 3: Video Signal Source Selection
Video Mode
RED Source Selection
Bits
xxxxxx00
xxxxxx01
xxxxxx10
xxxxxx11
Video Mode
CVBS Source Selection
Bits
xxxx00xx
xxxx01xx
xxxx10xx
xxxx11xx
Video Mode
BLUE Source Selection
Bits
xx00xxxx
xx01xxxx
xx10xxxx
xx11xxxx
Video Mode
GREEN Source Selection
Bits
00xxxxxx
01xxxxxx
10xxxxxx
11xxxxxx
GN_OUT
GN1
GN2
GN3
Not Used
RED_OUT
RD1
RD2
RD3
0V
CVBS_OUT
CVBS1
CVBS2
CVBS3
0V
BLUE_OUT
BL1
BL2
BL3
0V
FB_OUT
FB1
FB2
FB3
Not Used
Page: 5 of 16
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.0
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
