CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
INPUT CHARACTERISTICS
R
IN
C
IN
Input Resistance
Input Capacitance
V
S
+ = 5V, V
S
- = GND, T
A
= +25°C, V
CM
= 2.5V, R
L
to 2.5V, A
V
= 1, Unless Otherwise Specified
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
Common Mode
3.5
0.5
MΩ
pF
OUTPUT CHARACTERISTICS
R
OUT
Output Resistance
A
V
= +1
30
mΩ
ENABLE (5962-0623501QPC ONLY)
t
EN
t
DS
Enable Time
Disable Time
200
25
ns
ns
AC PERFORMANCE
BW
-3dB Bandwidth
A
V
= +1, R
F
= 0Ω, C
L
= 5pF
A
V
= -1, R
F
= 1kΩ, C
L
= 5pF
A
V
= +2, R
F
= 1kΩ, C
L
= 5pF
A
V
= +10, R
F
= 1kΩ, C
L
= 5pF
BW
Peak
GBWP
PM
SR
t
R
t
F
OS
t
PD
t
S
dG
dP
e
N
i
N
+
i
N
-
±0.1dB Bandwidth
Peaking
Gain Bandwidth Product
Phase Margin
Slew Rate
Rise Time
Fall Time
Overshoot
Propagation Delay
0.1% Settling Time
Differential Gain
Differential Phase
Input Noise Voltage
Positive Input Noise Current
Negative Input Noise Current
R
L
= 1kΩ, C
L
= 5pF
A
V
= 2, R
L
= 100Ω, V
OUT
= 0.5V to 4.5V
2.5V
STEP
, 20% to 80%
2.5V
STEP
, 20% to 80%
200mV step
200mV step
200mV step
A
V
= +2, R
F
= 1kΩ, R
L
= 150Ω
A
V
= +2, R
F
= 1kΩ, R
L
= 150Ω
f = 10kHz
f = 10kHz
f = 10kHz
A
V
= +1, R
F
= 0Ω, C
L
= 5pF
A
V
= +1, R
L
= 1kΩ, C
L
= 5pF
500
140
165
18
35
1
200
55
600
4
2
10
1
15
0.01
0.01
12
1.7
1.3
MHz
MHz
MHz
MHz
MHz
dB
MHz
°
V/µs
ns
ns
%
ns
ns
%
°
nV/√Hz
pA/√Hz
pA/√Hz
2
FN6472.1
May 11, 2007
5962-0623501QPC, 5962-0623502QPC
Pin Descriptions
PART
5962-0623501QPC
1, 5
2
3
4
6
7
8
5962-0623502QPC
1, 5, 8
2
3
4
6
7
PIN NAME
NC
IN-
IN+
VS-
OUT
VS+
ENABLE
Not connected
Inverting input
Non-inverting input
Negative power supply
Amplifier output
Positive power supply
Enable and disable input
FUNCTION
Simplified Schematic Diagram
V
S+
I1
I2
R6
R7
R8
Q5
R3
R1
Q1
Q2
R2
IN-
Q6
V
BIAS1
Q7
IN+
DIFFERENTIAL TO
SINGLE ENDED
DRIVE
GENERATOR
Q3
Q4
Q8
R4
R5
V
S-
OUT
V
BIAS2
R9
3
FN6472.1
May 11, 2007
5962-0623501QPC, 5962-0623502QPC
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
-D-
BASE
METAL
M
-B-
bbb S C A - B S
BASE
PLANE
SEATING
PLANE
S1
b2
b
A A
D
S2
-C-
Q
A
L
D S
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D8.3
MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
SYMBOL
A
b
b1
b2
b3
c
c1
D
E
e
eA
eA/2
L
Q
S1
S2
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.220
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
5.59
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
2.54 BSC
7.62 BSC
3.81 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
8
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 4/94
E
e
A
e
e
A/2
c
0.100 BSC
0.300 BSC
0.150 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
8
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
ccc M C A - B S D S
aaa
M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
α
aaa
bbb
ccc
M
N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
