5610
2k/8k COFDM Demodulator/FEC
Advanced Information
GENERAL DESCRIPTION
The 5610 is a low cost, low power, single
chip COFDM demodulator/FEC compliant to
ETSI specification for digital terrestrial
television broadcasting (ETS 300 744). The
device receives a 4.57 MHz IF signal and
performs analog-to-digital conversion,
COFDM processing and forward error
correction to provide an MPEG-2 transport
stream output. The COFDM processing
includes selectable programmable analog
interference suppression digital filters, I/Q
digital frequency and time acquisition, 2k &
8k FFT, pilot processing and channel
equalization, and demodulation. The design
also includes status monitoring and an I
2
C
or 3-wire serial interface pass through port
to control an analog front-end. Typical
applications for the 5610 include DVB-T set-
top box and integrated digital terrestrial
televisions.
FEATURES
• 2k/8k FFT processor
• ETS 300 744 compliant demodulation:
Non-hierarchical QPSK, 16-QAM, 64-QAM
Hierachical 16-QAM, 64-QAM
• Automatically detects all guard intervals
(1/32, 1/16, 1/8, 1/4)
• Supports 8,7, and 6 MHz channels with a single
36.5714 MHz crystal
–
no VCXO required
• Selectable adjacent and co-channel interference
suppression filters
• Programmable IF spectrum inversion
• Polarity programmable AGC control signal
• 9-bit ADC with single-ended or differential input
• I
2
C serial port control
• I
2
C or 3-wire pass-through port for tuner control
• Decoded TPS data and BER via I
2
C
• Power supply: 2.5V, 3.3V/2.5V (digital I/O)
• Low power dissipation: 630 mW typical
•
80 pin MQFP package
May 2000
I2C
interface
XA1
T L
XA2
T L
PLL
I2C/3-wire
Slave Interface
SSCL
SSDA
SSLD
SCL
SDA
A
0
A
1
Status
18.29 MHz
E TL
XCK
(Option)
A CN
DI P
A CN
DI N
AC
D
ADC
Bypass
ADCD[8:0]
ADC MODE[1:0]
Selectable
ACI,CCI
Suppression
Filter
FEC
Inter
face
Viterbi
Sync & De-interleave
ACU
GO T
AGC
(PWM)
OFDM
Demodulator Core
Reed Solomon
De-randomiser
TS CLOCK
TS DATA[7:0]
TS SYNC
TS VALID
TS ERROR
VITERBI LOCK
RS LOCK
5610 Functional block diagram
AGC LOCK
PLL LOCK
TPS LOCK
SSLD2
5610
2k/8k COFDM Demodulator/FEC
APPLICATION CIRCUIT (evaluation board available upon request)
Low Current
LEDs
(2 mA)
RESET
I2C ADDRESS
PROGRAMMABLE BITS
A0/A1
TBD
I2C DATA
I2C CLOCK
+2.5V Digital SUPPLY
+2.5V Digital RETURN
+2.5V/3.3V I/O RETURN
+2.5V/3.3V I/O SUPPLY
LD2 (for 3-wire)
LD1 (for 3-wire)
SDATA
SCLOCK
OPTIONAL
18.29 MHz
ADC CLOCK
ANALOG
FRONT-END
20pF
R
IFout+
Optional
Differential Input
R C1
2.5V
0.1
uF
AGC
390
pF
C2
C2
4.7k
1.25V
Ref.
Diode
(5%)
36.5714
MHz
20pF
C1
L
C3
R
R
50k
1k
IFout-
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSLD
SSLD2
PLL LOCK
AGC LOCK
DVDD
DGND
IGND
IVDD
TPS LOCK
VITERBI LOCK
RS LOCK
RESETN
A0
A1
SDA
SCL
+2.5V
Analog RETURN
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
+2.5V
Analog SUPPLY
SSDA
SSCL
AGND4
AVDD4
NC
EXTCLK
AGND3
AVDD3
XTAL1
XTAL2
AVDD2
AGND2
AVDD1
AGND1
ADCINP
ADCINN
AGND0
AVDD0
VREF
REXT
VREFOUT
ADC MODE[0]
AGC
ADC MODE[1]
5610
IGND
IVDD
TSDATA[7]
TSDATA[6]
TSDATA[5]
TSDATA[4]
TSDATA[3]
TSDATA[2]
IGND
IVDD
TSDATA[1]
TSDATA[0]
TSERROR
TSVALID
TSSYNC
IVDD
IGND
TSCLOCK
IGND
NC
NC
NC
DGND
DVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TSDATA[7]
TSDATA[6]
TSDATA[5]
TSDATA[4]
TSDATA[3]
TSDATA[2]
TSDATA[1]
TSDATA[0]
TSERROR
TSVALID
TSSYNC
TSCLOCK
TO
MPEG-2
DECODER
ADC MODE SELECT
(FOR DEBUG)
For more information, please contact:
Hiroshi Kamata at: hiroshi.kamata@tsc.tdk.com
or Tim Jackson at: tim.jackson@tsc.tdk.com; tel: 714-508-8718
PART DESCRIPTION
5610 2k/8k COFDM
Demodulator FEC
ORDER NO.
5610-CG
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
INTERNAL ADC OUTPUT/
EXTERNAL ADC INPUT
(FOR DEBUG)
ADCD[8]
ADCD[7]
ADCD[6]
ADCD[5]
ADCD[4]
ADCD[3]
IGND
IVDD
ADCD[2]
ADCD[1]
ADCD[0]
NC
NC
NC
NC
NC
PACKAGE MARK
5610-CG
Advanced Information:
The Advanced Information data sheet is to be approved for Beta Site and advanced customer
information purposes only. It is not intended to replace the electrical specification for the specific device it represents.
This document will be updated and converted into a Final (Preliminary Data Sheet) upon completion of Design
Engineering Validation. Design Engineering should review this documentation for its accuracy to the definition and the
design goals for the product it represents.
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of
patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents,
patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in
specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current
before placing orders.
TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877,
http://www.tsc.tdk.com
©
2000 TDK Semiconductor Corporation
2000/05/11 rev. A2
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