MMDF2C03HD
Power MOSFET
2 Amps, 30 Volts
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain-to-source diode has a very low reverse recovery time. These
devices are designed for use in low voltage, high speed switching
applications where power efficiency is important. Typical applications
are dc-dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
Features
Complementary SO−8, Dual
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2 AMPERES, 30 VOLTS
R
DS(on)
= 70 mW (N-Channel)
R
DS(on)
= 200 mW (P-Channel)
N−Channel
D
P−Channel
D
•
•
•
•
•
•
•
•
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
Miniature SO-8 Surface Mount Package
−
Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
I
DSS
Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO-8 Package Provided
This is a Pb−Free Device
Rating
Symbol
V
DSS
V
GS
N−Channel
P−Channel
N−Channel
P−Channel
I
D
I
DM
T
J
, T
stg
P
D
R
qJA
E
AS
324
324
T
L
260
°C
Value
30
±
20
4.1
3.0
21
15
−
55 to 150
2.0
62.5
Unit
Vdc
Vdc
A
G
S
G
S
MARKING
DIAGRAM
8
8
1
SO−8
CASE 751
STYLE 14
1
D2C03
AYWWG
G
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted) (Note 1)
Drain−to−Source Voltage
Gate−to−Source Voltage
Drain Current
−
Continuous
Drain Current
−
Pulsed
D2C03 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Operating and Storage Temperature Range
Total Power Dissipation @ T
A
= 25°C (Note 2)
Thermal Resistance, Junction−to−Ambient
(Note 2)
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 30 V, V
GS
= 5.0 V, Peak I
L
= 9.0 Apk,
L = 8.0 mH, R
G
= 25
W)
N−Channel
(V
DD
= 30 V, V
GS
= 5.0 V, Peak I
L
= 6.0 Apk,
L = 18 mH, R
G
= 25
W)
P−Channel
Max Lead Temperature for Soldering, 0.0625″
from case. Time in Solder Bath is 10 seconds
°C
W
°C/W
mJ
PIN ASSIGNMENT
N−Source
N−Gate
P−Source
P−Gate
1
2
3
4
8
7
6
5
N−Drain
N−Drain
P−Drain
P−Drain
ORDERING INFORMATION
Device
MMDF2C03HDR2G
Package
Shipping
†
SO−8
2500 Tape & Reel
(Pb−Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Negative signs for P−Channel device omitted for clarity.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with
one die operating, 10 sec. max.
©
Semiconductor Components Industries, LLC, 2011
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
October, 2011
−
Rev. 8
1
Publication Order Number:
MMDF2C03HD/D
MMDF2C03HD
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted) (Note 3)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 4)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 3.0 Adc)
(V
GS
= 10 Vdc, I
D
= 2.0 Adc)
Drain−to−Source On−Resistance
(V
GS
= 4.5 Vdc, I
D
= 1.5 Adc)
(V
GS
= 4.5 Vdc, I
D
= 1.0 Adc)
Forward Transconductance
(V
DS
= 3.0 Vdc, I
D
= 1.5 Adc)
(V
DS
= 3.0 Vdc, I
D
= 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(V
DS
= 10 Vdc, I
D
= 3.0 Adc,
V
GS
= 10 Vdc)
(V
DS
= 24 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc)
(V
DD
= 15 Vdc, I
D
= 3.0 Adc,
V
GS
= 10 Vdc, R
G
= 9.1
W)
(V
DD
= 15 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc, R
G
= 6.0
W)
(V
DD
= 15 Vdc, I
D
= 3.0 Adc,
V
GS
= 4.5 Vdc, R
G
= 9.1
W)
(V
DD
= 15 Vdc, I
D
= 2.0 Adc,
V
GS
= 4.5 Vdc, R
G
= 6.0
W)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
3. Negative signs for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
5. Switching characteristics are independent of operating junction temperature.
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
12
16
65
18
16
63
19
194
8.0
9.0
15
10
30
81
23
192
11.5
14.2
1.5
1.1
3.5
4.5
2.8
3.5
24
32
130
36
32
126
38
390
16
18
30
20
60
162
46
384
16
19
−
−
−
−
−
−
nC
ns
(V
DS
= 24 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
(N)
(P)
(N)
(P)
(N)
(P)
−
−
−
−
−
−
450
397
160
189
35
64
630
550
225
250
70
126
pF
V
GS(th)
R
DS(on)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
1.0
1.0
−
−
−
−
2.0
2.0
1.7
1.5
0.06
0.17
0.065
0.225
3.6
3.4
3.0
2.0
0.070
0.200
0.075
0.300
−
−
Vdc
W
V
(BR)DSS
I
DSS
I
GSS
−
(N)
(P)
−
30
−
−
−
−
−
−
−
−
1.0
1.0
100
Vdc
mAdc
nAdc
Symbol
Polarity
Min
Typ
Max
Unit
R
DS(on)
W
g
FS
mhos
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2
MMDF2C03HD
ELECTRICAL CHARACTERISTICS
−
continued
(T
A
= 25°C unless otherwise noted) (Note 6)
Characteristic
SOURCE−DRAIN DIODE CHARACTERISTICS
(T
C
= 25°C)
Forward Voltage (Note 7)
Reverse Recovery Time
(I
S
= 3.0 Adc, V
GS
= 0 Vdc)
(I
S
= 2.0 Adc, V
GS
= 0 Vdc)
V
SD
t
rr
t
a
(I
F
= I
S
, dI
S
/dt = 100 A/ms)
Reverse Recovery Storage
Charge
6. Negative signs for P−Channel device omitted for clarity.
7. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
t
b
Q
RR
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
−
−
−
−
−
−
−
−
−
−
0.82
1.82
24
42
17
16
7.0
26
0.025
0.043
1.2
2.0
−
−
−
−
−
−
−
−
mC
Vdc
ns
Symbol
Polarity
Min
Typ
Max
Unit
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
6
I D , DRAIN CURRENT (AMPS)
5
4
3
2
2.9 V
1
0
2.7 V
2.5 V
0
0.2
0.6 0.8
1
1.4 1.6
0.4
1.2
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1.8
2
0
0
0.2
V
GS
= 10 V
4.5 V
4.3 V
4.1 V
3.9 V
3.7 V
3.3 V
3.5 V
4
T
J
= 25°C
I D , DRAIN CURRENT (AMPS)
3
P−Channel
V
GS
= 10 V 4.5 V
3.9 V
3.3 V
3.7 V 3.5 V
T
J
= 25°C
3.1 V
2
3.1 V
2.9 V
1
2.7 V
2.5 V
1
1.2 1.4
0.4
0.6
0.8
1.6
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1.8
2
Figure 1. On−Region Characteristics
6
V
DS
≥
10 V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
5
4
T
J
= 100°C
3
2
1
0
- 55°C
25°C
3
4
Figure 1. On−Region Characteristics
V
DS
≥
10 V
2
T
J
= 100°C
25°C
1
- 55°C
2
2.5
3
3.5
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
4
0
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
Figure 2. Transfer Characteristics
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3
MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
0.6
0.5
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
10
I
D
= 1.5 A
T
J
= 25°C
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
P−Channel
0.6
0.5
0.4
0.3
0.2
0.1
0
I
D
= 1 A
T
J
= 25°C
0
1
3
4
5
6
7
8
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
2
9
10
Figure 3. On−Resistance versus
Gate−To−Source Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
0.08
T
J
= 25°C
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
0.30
Figure 3. On−Resistance versus
Gate−To−Source Voltage
T
J
= 25°C
0.25
V
GS
= 4.5 V
0.20
10 V
0.15
0.07
V
GS
= 4.5
0.06
10 V
0.05
0
0.5
1
1.5
2
2.5
3
I
D
, DRAIN CURRENT (AMPS)
0.10
0
0.5
1
2.5
3
1.5
2
I
D
, DRAIN CURRENT (AMPS)
3.5
4
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
RDS(on) , DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
V
GS
= 10 V
I
D
= 1.5 A
1.5
1.6
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
V
GS
= 10 V
I
D
= 2 A
1.4
1.2
1.0
1.0
0.5
0.8
0
- 50
- 25
0
25
50
75
100
125
150
0.6
- 50
- 25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 5. On−Resistance Variation with
Temperature
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4
MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
100
V
GS
= 0 V
T
J
= 125°C
1000
V
GS
= 0 V
P−Channel
I DSS , LEAKAGE (nA)
I DSS , LEAKAGE (nA)
10
100°C
100
T
J
= 125°C
100°C
1
0
5
10
15
20
25
30
10
0
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
5
10
15
20
25
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
30
Figure 6. Drain−To−Source Leakage
Current versus Voltage
Figure 6. Drain−To−Source Leakage
Current versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
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5
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