There are two limitations on the power handling ability of
a transistor: average junction temperature and secondary
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 10 is based on T
J(pk)
= 150°C; T
C
is
variable depending on conditions. Secondary breakdown
pulse limits are valid for duty cycles to 10% provided T
J(pk)
v
150°C. T
J(pk)
may be calculated from the data in
Figure 12. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by secondary breakdown.
Figure 11. Power Derating
1.0
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
D = 0.5
0.1
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.001
R
qJA
(t) = r(t)
q
JA
q
JA
= 165°C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
A
= P
(pk)
q
JA
(t)
0.01
0.1
t, TIME (seconds)
1.0
10
P
(pk)
0.01
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
100
1000
0.0001
0.0001
0.001
Figure 12. Thermal Response
http://onsemi.com
4
MMJT9410
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L
D
b1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
MILLIMETERS
NOM
MAX
1.63
1.75
0.06
0.10
0.75
0.89
3.06
3.20
0.29
0.35
6.50
6.70
3.50
3.70
2.30
2.40
0.94
1.05
1.75
2.00
7.00
7.30
10°
−
INCHES
NOM
0.064
0.002
0.030
0.121
0.012
0.256
0.138
0.091
0.037
0.069
0.276
−
4
H
E
1
2
3
E
b
e1
e
q
C
DIM
A
A1
b
b1
c
D
E
e
e1
L1
H
E
q
MIN
1.50
0.02
0.60
2.90
0.24
6.30
3.30
2.20
0.85
1.50
6.70
0°
MIN
0.060
0.001
0.024
0.115
0.009
0.249
0.130
0.087
0.033
0.060
0.264
0°
MAX
0.068
0.004
0.035
0.126
0.014
0.263
0.145
0.094
0.041
0.078
0.287
10°
A
0.08 (0003)
A1
L1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
SOLDERING FOOTPRINT*
3.8
0.15
2.0
0.079
2.3
0.091
2.3
0.091
6.3
0.248
2.0
0.079
1.5
0.059
mm
inches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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