Si4539DY
January 2001
Si4539DY
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
N-Channel 7.0 A,30 V, R
DS(ON)
=0.028
Ω
@ V
GS
=10 V
R
DS(ON)
=0.040
Ω
@ V
GS
= 4.5 V.
P-Channel -5.0 A,-30 V,R
DS(ON)
=0.052
Ω
@ V
GS
=-10 V
R
DS(ON)
=0.080
Ω
@ V
GS
=-4.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
SOT-23
TM
SuperSOT -6
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D2
D1
D1
D2
5
4
3
2
1
9
53
4
S2
G2
6
7
8
SO-8
pin
1
S1
G1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
P
D
T
A
= 25°C unless otherwise noted
N-Channel
30
20
(Note 1a)
P-Channel
-30
-20
-5
-20
2
Units
V
V
A
7
20
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
W
1.6
1
0.9
-55 to 150
°C
T
J
,T
STG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R
θJA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
© 2001 Fairchild Semiconductor International
Si4539DY Rev. A
Si4539DY
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25
o
C
I
D
= -250 µA, Referenced to 25
o
C
I
DSS
I
GSSF
I
GSSR
V
GS(th)
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
V
DS
= -24 V, V
GS
= 0 V
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25
o
C
I
D
= -250 µA, Referenced to 25
o
C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 7.0 A
V
GS
= 4.5 V, I
D
= 6.0 A
V
GS
= -10 V, I
D
= -5.0 A
V
GS
= -4.5 V, I
D
= - 4.0 A
I
D(on)
g
FS
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
V
GS
= -10 V, V
DS
= -5 V
Forward Transconductance
V
DS
= 5 V, I
D
= -7 A
V
DS
= -5 V, I
D
= -5 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
N-Ch
P-Ch
N-Ch
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
P-Ch
N-Ch
P-Ch
650
730
345
400
90
90
pF
pF
pF
N-Ch
P-Ch
N-Ch
P-Ch
20
-20
15
8
S
S
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
All
All
30
-30
30
-25
1
-1
100
-100
µA
µA
nA
nA
V
V
mV/
o
C
∆
BV
DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
1
-1
1.7
-1.5
-4.4
3.2
0.024
0.035
0.044
0.068
0.028
0.04
0.052
0.08
A
3
-3
V
V
mV/
o
C
∆
V
GS(th)
/
∆
T
J
Gate Threshold Voltage Temp. Coefficient
Ω
Input Capacitance
Reverse Transfer Capacitance
Si4539DY Rev. A
Si4539DY
Electrical Characteristics
(continued)
SWITCHING CHARACTERISTICS
Symbol
t
D(on)
Parameter
Turn - On Delay Time
(Note 2)
Conditions
V
DS
= 10 V, I
D
= 1 A
V
GS
= 10 V , R
GEN
= 6
Ω
Type
N-Ch
P-Ch
N-Ch
P-Ch
Min
Typ
8
11
14
10
23
90
9
55
18
19
3.2
3.5
4.3
3.6
Max
16
20
25
18
37
125
18
80
26
27
Units
ns
t
r
t
D(off)
Turn - On Rise Time
ns
Turn - Off Delay Time
V
DS
= -10 V, I
D
= -1 A
V
GS
= -10 V , R
GEN
= 6
Ω
N-Ch
P-Ch
N-Ch
P-Ch
ns
t
f
Q
g
Q
gs
Q
gd
Turn - Off Fall Time
ns
Total Gate Charge
V
DS
= 10 V, I
D
= 7 A,
V
GS
= 10 V
N-Ch
P-Ch
N-Ch
nC
Gate-Source Charge
V
DS
= -10 V, I
D
= -5 A,
Gate-Drain Charge
V
GS
= -10 V
nC
P-Ch
N-Ch
P-Ch
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
N-Ch
P-Ch
1.3
-1.3
0.75
-0.75
1.2
-1.2
A
A
V
V
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.3 A
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
(Note 2)
N-Ch
P-Ch
a. 78
O
C/W on a 0.5 in
2
pad of 2oz copper.
b. 125
O
C/W on a 0.02 in
2
pad of 2oz copper.
c. 135
O
C/W on a 0.003 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%..
Si4539DY Rev. A
Si4539DY
Typical Electrical Characteristics: N-Channel
30
I
D
, DRAIN-SOURCE CURRENT (A)
2.4
5.5V
R
DS(ON)
, NORMALIZED
24
4.5V
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 10V
2
18
4.0V
V
GS
= 4.0V
1.6
4.5 V
5.0V
6.0 V
7.0V
10V
12
3.5V
6
1.2
3.0V
0
0
1
2
3
4
5
0.8
0
6
12
18
24
30
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.8
DRAIN-SOURCE ON-RESISTANCE
0.15
I
D
= 7A
1.6
1.4
1.2
1
0.8
0.6
-50
I
D
= 3A
R
DS(ON)
, ON-RESISTANCE (OHM)
V
GS
= 10V
0.12
R
DS(ON)
, NORMALIZED
0.09
0.06
T
A
= 125°C
0.03
T
A
= 25°C
0
2
4
6
8
10
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
V
DS
= 10V
I
D
, DRAIN CURRENT (A)
25
20
15
10
I
S
, REVERSE DRAIN CURRENT (A)
30
20
V
GS
= 0V
TJ = 125°C
1
25°C
0.1
-55°C
0.01
T = 125°C
J
5
25°C
-55°C
0.001
0
0.0001
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
Si4539DY Rev. A
Si4539DY
Typical Electrical Characteristics: N-Channel
(continued)
10
V
GS
, GATE-SOURCE VOLTAGE (V)
2000
I
D
= 7A
8
V
DS
= 5V
CAPACITANCE (pF)
1200
10V
15V
800
C
iss
Coss
6
400
4
200
2
100
f = 1 MHz
V
GS
= 0 V
0.2
0.5
1
2
5
Crss
0
0
2
4
6
8
10
12
Q
g
, GATE CHARGE (nC)
50
0.1
10
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
50
30
I
D
, DRAIN CURRENT (A)
10
5
2
1
0.5
MIT
) LI
(ON
S
RD
100
1m
s
10m
30
us
25
20
15
10
5
0
0.01
SINGLE PULSE
R
θ
JA
=135 °C/W
T
A
= 25°C
10
0m
s
1s
0.1
0.05
V
GS
=10V
SINGLE PULSE
R
θ
JA
= 135° C/W
T
A
= 25°C
A
0.2
0.5
1
2
5
10s
DC
POWER (W)
s
0.01
0.1
0.1
0.5
10
50 100
300
10
30
50
SINGLE PULSE TIME (SEC)
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
Si4539DY Rev. A
嵌入式系统
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