M58MR064C
M58MR064D
64 Mbit (4Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory
s
SUPPLY VOLTAGE
– V
DD
= V
DDQ
= 1.65V to 2.0V for Program,
Erase and Read
– V
PP
= 12V for fast Program (optional)
s
s
MULTIPLEXED ADDRESS/DATA
SYNCHRONOUS / ASYNCHRONOUS READ
– Burst mode Read: 54MHz
– Page mode Read (4 Words Page)
– Random Access: 100ns
FBGA
TFBGA48 (ZC)
10 x 4 ball array
s
PROGRAMMING TIME
– 10µs by Word typical
– Two or four words programming option
s
MEMORY BLOCKS
– Dual Bank Memory Array: 16/48 Mbit
– Parameter Blocks (Top or Bottom location)
Figure 1. Logic Diagram
s
DUAL OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
VDD VDDQ VPP
6
A16-A21
W
E
G
RP
WP
L
K
M58MR064C
M58MR064D
BINV
WAIT
16
ADQ0-ADQ15
s
PROTECTION/SECURITY
– All Blocks protected at Power-up
– Any combination of Blocks can be protected
– 64 bit unique device identifier
– 64 bit user programmable OTP cells
– One parameter block permanently lockable
s
s
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58MR064C: 88DCh
– Bottom Device Code, M58MR064D: 88DDh
s
VSS
AI90087
March 2002
1/52
M58MR064C, M58MR064D
Figure 2. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
DU
DU
B
DU
DU
C
WAIT
A21
VSS
K
VDD
W
VPP
A19
A17
NC
D
VDDQ
A16
A20
L
BINV
RP
WP
A18
E
VSS
E
VSS
ADQ7
ADQ6
ADQ13
ADQ12
ADQ3
ADQ2
ADQ9
ADQ8
G
F
ADQ15
ADQ14
VSS
ADQ5
ADQ4
ADQ11
ADQ10
VDDQ
ADQ1
ADQ0
G
DU
DU
H
DU
DU
AI90088
DESCRIPTION
The M58MR064 is a 64 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-by-
Word basis using a 1.65V to 2.0V V
DD
supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated inter-
nally. The device supports synchronous burst read
and asynchronous read from all the blocks of the
memory array; at power-up the device is config-
ured for page mode read. In synchronous burst
mode, a new data is output at each clock cycle for
frequencies up to 54MHz.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power-up.
Blocks can be unprotected to make changes in the
application and then re-protected.
A parameter block ”Security block” can be perma-
nently protected against programming and erasing
in order to increase the data security. An optional
12V V
PP
power supply is provided to speed up the
program phase at costumer production. An inter-
nal command interface (C.I.) decodes the instruc-
tions to access/modify the memory content. The
program/erase controller (P/E.C.) automatically
executes the algorithms taking care of the timings
necessary for program and erase operations. Two
status registers indicate the state of each bank.
Instructions for Read Array, Read Electronic Sig-
nature, Read Status Register, Clear Status Regis-
ter, Write Read Configuration Register, Program,
Block Erase, Bank Erase, Program Suspend, Pro-
gram Resume, Erase Suspend, Erase Resume,
Block Protect, Block Unprotect, Block Locking,
Protection Program, CFI Query, are written to the
memory through a Command Interface (C.I.) using
standard micro-processor write timings.
The memory is offered in TFBGA48, 0.5 mm ball
pitch packages and it is supplied with all the bits
erased (set to ’1’).
2/52
M58MR064C, M58MR064D
Table 1. Signal Names
A16-A21
ADQ0-ADQ15
E
G
W
RP
WP
K
L
WAIT
BINV
V
DD
V
DDQ
V
PP
V
SS
DU
NC
Address Inputs
Data Input/Outputs or Address
Inputs, Command Inputs
Chip Enable
Output Enable
Write Enable
Reset/Power-down
Write Protect
Burst Clock
Latch Enable
Wait Data in Burst Mode
Bus Invert
Supply Voltage
Supply Voltage for Input/Output
Buffers
Optional Supply Voltage for
Fast Program & Erase
Ground
Don’t Use as Internally Connected
Not Connected Internally
Organization
The M58MR064 is organized as 4Mb by 16 bits.
The first sixteen address lines are multiplexed with
the Data Input/Output signals on the multiplexed
address/data bus ADQ0-ADQ15. The remaining
address lines A16-A21 are the MSB addresses.
Chip Enable E, Output Enable G and Write Enable
W inputs provide memory control.
The clock K input synchronizes the memory to the
microprocessor during burst read.
Reset RP is used to reset all the memory circuitry
and to set the chip in power-down mode if a proper
setting of the Read Configuration Register en-
ables this function.
WAIT output indicates to the microprocessor the
status of the memory during the burst mode oper-
ations.
Memory Blocks
The device features asymmetrically blocked archi-
tecture. M58MR064 has an array of 135 blocks
and is divided into two banks A and B, providing
Dual Bank operations. While programming or
erasing in Bank A, read operations are possible
into Bank B or vice versa. Only one bank at the
time is allowed to be in program or erase mode. It
is possible to perform burst reads that cross bank
boundaries.
The memory features an erase suspend allowing
reading or programming in another block. Once
suspended the erase can be resumed. Program
can be suspended to read data in another block
and then resumed. The Bank Size and sectoriza-
tion are summarized in Table 3. Parameter Blocks
are located at the top of the memory address
space for the M58MR064C, and at the bottom for
the M58MR064D. The memory maps are shown in
Figure 3.
Value
–40 to 85
–40 to 125
–55 to 155
–0.5 to V
DDQ
+0.5
–0.5 to 2.7
–0.5 to 13
Unit
°C
°C
°C
V
V
V
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (3)
V
DD
, V
DDQ
V
PP
Parameter
Ambient Operating Temperature
(2)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Program Voltage
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Depends on range.
3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3/52
M58MR064C, M58MR064D
The architecture includes a 128 bits Protection
register that is divided into two 64-bits segments.
In the first one is written a unique device number,
while the second one is programmable by the us-
er. The user programmable segment can be per-
manently protected programming the bit 1 of the
Protection Lock Register (see protection register
and Security Block). The parameter block (# 0) is
a security block. It can be permanently protected
Table 3. Bank Size and Sectorization
Bank Size
Bank A
Bank B
16 Mbit
48 Mbit
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
31 blocks of 32 KWord
96 blocks of 32 KWord
by the user programming the bit 2 of the Protection
Lock Register.
Block protection against Program or Erase pro-
vides additional data security. All blocks are pro-
tected and unlocked at Power-up. Instructions are
provided to protect or un-protect any block in the
application. A second register locks the protection
status while WP is low (see Block Locking descrip-
tion).
Figure 3. Memory Map
Top Boot Block
Address lines A21-A0
000000h
007FFFh
Bank B
512 Kbit or
32 KWord
Total of 96
Main Blocks
000000h
000FFFh
Bottom Boot Block
Address lines A21-A0
64 Kbit or
4 KWord
Total of 8
Parameter
Blocks
007000h
Bank A
512 Kbit or
32 KWord
Total of 31
Main Blocks
007FFFh
008000h
00FFFFh
64 Kbit or
4 KWord
512 Kbit or
32 KWord
Total of 31
Main Blocks
2F8000h
2FFFFFh
300000h
307FFFh
512 Kbit or
32 KWord
3F0000h
Bank A
3F7FFFh
3F8000h
3F8FFFh
512 Kbit or
32 KWord
64 Kbit or
4 KWord
Total of 8
Parameter
Blocks
0F8000h
0FFFFFh
100000h
107FFFh
Bank B
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Total of 96
Main Blocks
3FF000h
3FFFFFh
64 Kbit or
4 KWord
3F8000h
3FFFFFh
512 Kbit or
32 KWord
AI90089
4/52
M58MR064C, M58MR064D
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs or Data Input/Output (ADQ0-
ADQ15).
When Chip Enable E is at V
IL
and Out-
put Enable G is at V
IH
the multiplexed address/
data bus is used to input addresses for the memo-
ry array, data to be programmed in the memory ar-
ray or commands to be written to the C.I. The
address inputs for the memory array are latched
on the rising edge of Latch Enable L. The address
latch is transparent when L is at V
IL
. In synchro-
nous operations the address is also latched on the
first rising/falling edge of K (depending on clock
configuration) when L is low. Both input data and
commands are latched on the rising edge of Write
Enable W. When Chip Enable E and Output En-
able G are at V
IL
the address/data bus outputs
data from the Memory Array, the Electronic Signa-
ture Manufacturer or Device codes, the Block Pro-
tection status the Read Configuration Register
status, the protection register or the Status Regis-
ter. The address/data bus is high impedance when
the chip is deselected, Output Enable G is at V
IH
,
or RP is at V
IL
.
Address Inputs (A16-A21).
The five MSB ad-
dresses of the memory array are latched on the
rising edge of Latch Enable L. In synchronous op-
eration these inputs are also latched on the first
rising/falling edge of K (depending on clock config-
uration) when L is low.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at V
IH
deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at V
IL
.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at V
IH
the outputs are High im-
pedance.
Write Enable (W).
This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP).
This input gives an addition-
al hardware protection level against program or
erase when pulled at V
IL
, as described in the Block
Lock instruction description.
Reset/Power-down Input (RP).
The RP input
provides hardware reset of the memory, and/or
Power-down functions, depending on the Read
Configuration Register status. Reset/Power-down
of the memory is achieved by pulling RP to V
IL
for
at least t
PLPH
. When the reset pulse is given, the
memory will recover from Power-down (when en-
abled) in a minimum of t
PHEL
, t
PHLL
or t
PHWL
(see
Table 31 and Figure 15) after the rising edge of
RP. Exit from Reset/Power-down changes the
contents of the Read Configuration Register bits
14 and 15, setting the memory in asynchronous
page mode read and power save function dis-
abled. All blocks are protected and unlocked after
a Reset/Power-down.
Latch Enable (L).
L latches the address bits
ADQ0-ADQ15 and A16-A21 on its rising edge.
The address latch is transparent when L is at V
IL
and it is inhibited when L is at V
IH
.
Clock (K).
The clock input synchronizes the
memory to the micro controller during burst mode
read operation; the address is latched on a K edge
(rising or falling, according to the configuration set-
tings) when L is at V
IL
. K is don’t care during asyn-
chronous page mode read and in write operations.
Wait (WAIT).
WAIT is an output signal used dur-
ing burst mode read, indicating whether the data
on the output bus are valid or a wait state must be
inserted. This output is high impedance when E or
G are high or RP is at V
IL
, and can be configured
to be active during the wait cycle or one clock cy-
cle in advance.
Bus Invert (BINV).
BINV is an input/output signal
used to reduce the amount of power needed to
switch the external address/data bus. The power
saving is achieved by inverting the data output on
ADQ0-ADQ15 every time this gives an advantage
in terms of number of toggling bits. In burst mode
read, each new data output from the memory is
compared with the previous data. If the number of
transitions required on the data bus is in excess of
8, the data is inverted and the BINV signal will be
driven by the memory at V
OH
to inform the receiv-
ing system that data must be inverted before any
further processing. By doing so, the actual transi-
tions on the data bus will be less than 8.
In a similar way, when a command is given, BINV
may be driven by the system at V
IH
to inform the
memory that the data input must be inverted.
Like the other input/output pins, BINV is high im-
pedance when the chip is deselected, output en-
able G is at V
IH
or RP is at V
IL
; when used as an
input, BINV must follow the same set-up and hold
timings of the data inputs.
V
DD
and V
DDQ
Supply Voltage (1.65V to 2.0V).
V
DD
is the main power supply for all operations
(Read, Program and Erase). V
DDQ
is the supply
voltage for Input and Output.
5/52
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