Datasheet> 器件分类 > 逻辑> 逻辑> HCF40160M013TR

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HCF40160M013TR: 产品描述4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, SO-16; 产品类别逻辑逻辑; 文件大小283KB，共14页; 制造商ST(意法半导体); 官网地址http://www.st.com/; 标准

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HCF40160M013TR概述

4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, SO-16

HCF40160M013TR规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	ST(意法半导体)
零件包装代码	SOIC
包装说明	SO-16
针数	16
Reach Compliance Code	compliant
Is Samacsys	N
计数方向	UP
系列	4000/14000/40000
JESD-30 代码	R-PDSO-G16
JESD-609代码	e4
长度	9.9 mm
负载电容（CL）	50 pF
负载/预设输入	YES
逻辑集成电路类型	DECADE COUNTER
最大频率@ Nom-Sup	2000000 Hz
工作模式	SYNCHRONOUS
位数	4
功能数量	1
端子数量	16
最高工作温度	125 °C
最低工作温度	-55 °C
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装等效代码	SOP16,.25
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
包装方法	TAPE AND REEL
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	5/15 V
传播延迟（tpd）	400 ns
认证状态	Not Qualified
座面最大高度	1.75 mm
最大供电电压 (Vsup)	20 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
触发器类型	POSITIVE EDGE
宽度	3.9 mm
最小 fmax	8 MHz
Base Number Matches	1

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HCF40160B

SYNCHRONOUS PROGRAMMABLE 4-BIT DECADE

COUNTER WITH ASYNCHRONOUS CLEAR

INTERNAL LOOK-AHEAD FOR FAST

COUNTING

CARRY OUTPUT FOR CASCADING

SYNCHRONOUSLY PROGRAMMABLE

LOW-POWER TTL COMPATIBILITY

STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

QUIESCENT CURRENT SPECIF. UP TO 20V

5V, 10V AND 15V PARAMETRIC RATINGS

INPUT LEAKAGE CURRENT

= 100nA (MAX) AT V

= 18V T

= 25°C

100% TESTED FOR QUIESCENT CURRENT

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DIP

SOP

ORDER CODES

PACKAGE

DIP

SOP

TUBE

HCF40160BEY

HCF40160BM1

T&R

HCF40160M013TR

DESCRIPTION

HCF40160B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.

HCF40160B is 4-bit synchronous programmable

counters. The CLEAR function is asynchronous. A

low level at the CLEAR input sets all four outputs

low regardless of the state of the CLOCK, LOAD

and ENABLE inputs. A low level at the LOAD

inputs disables the counter and causes the output

to agree with the set-up data after the following

CLOCK pulse regardless of the condition of the

ENABLE inputs. Two count-enable inputs and a

carry output (COUT) are instrumental in

accomplishing this function. The carry look-ahead

circuitry provides for cascading counter for n-bit

synchronous application without additional gating.

Counting is enabled when both the PE and TE

inputs are high. The TE input is fed forward to

enable COUT. This enable output produces a

positive

output

pulse

with

duration

approximately equal to the positive portion of the

Q1 output. This positive overflow carry pulse can

be used to enable successive cascaded stages.

Logic transitions at the PE and TE inputs may

occur when the clock is either high or low.

PIN CONNECTION

September 2002

1/14

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