PWR-82341
SMART POWER H-BRIDGE MOTOR
DRIVE
DESCRIPTION
The PWR-82341 is a smart Power
H-Bridge Motor Drive hybrid. The
PWR-82341 uses a MOSFET output
stage with a 100Vdc rating, and can
deliver 5A continuous, 10 A peak cur-
rent to the load.
This Smart Power Motor Drive has
CMOS Schmitt Trigger inputs for high
noise immunity. High and low-side
input logic signals are XOR’d in each
phase to prevent simultaneous turn
on of in-line transistors, thus eliminat-
ing a shoot through condition.
The internal logic controls the high
and low-side gate drivers for each
phase and can operate from +5 to
+15 V logic levels. An internal charge
pump circuit provides the required
voltage to the high-side gate drives.
This ensures constant output perfor-
mance for switching frequencies from
DC to 50 kHz.
APPLICATIONS
Packaged in a small case, these
hybrids are an excellent choice for
high performance, high-reliability
motor drives for Military and
Aerospace servo-amps and speed
controls.
Among the many applications are
robotics; electro-mechanical valve
assemblies; actuator systems;
antenna and radar positioning; fan
and blower motors for environmental
conditioning; position control of mini-
subs, drones, and RPV’s; and com-
pressor motors for cryogenic coolers.
The PWR-82341 hybrid is ideal for
harsh military environments where
shock, vibration, and temperature
extremes are evident, such as missile
applications including fin actuators
and I. seeker head movement. The
PWR-82341 operates over the -55°C
to +125°C temperature range and is
available with military processing.
FEATURES
•
Small size (1.8" x 1.4" x 0.25")
•
100 VDC Rating
•
5 A Continuous, 10 A peak
Capability
•
High-Efficiency MOSFET Drive
Stage
•
Direct Drive from PWM
•
Drive Brush or Brushless DC
Motors
•
Four Quadrant Operation
•
Military Processing Available
32
34
4
5, 11, 16
6
+CAP
-CAP
V+
GND
V
LPI
V
CA
DRIVE
A
V
SS
V
CC
V
CC
30, 31
CHARGE PUMP
8
10
V
UA
V
LA
27, 28
DIGITAL
CONTROL
AND
PROTECTION
CIRCUITRY
V
UB
V
LB
25, 26
23, 24
V
CA
13
15
DRIVE
B
V
SS
21, 22
12
V
Sd
18, 19
FIGURE 1. PWR-82341 BLOCK DIAGRAM
©
1992, 1999 Data Device Corporation
TABLE 1. PWR-82341 ABSOLUTE MAXIMUM RATINGS
(Tc = +25°C Unless Otherwise Specified)
PARAMETER
SUPPLY VOLTAGE
INPUT VOLTAGE
LOGIC POWER-IN VOLTAGE
INPUT LOGIC VOLTAGE
OUTPUT CURRENT
Continuous
Peak
OPERATING FREQUENCY
CASE OPERATING TEMPERATURE
CASE STORAGE TEMPERATURE RANGE
SYMBOL
V
CC
V+
V
LPI
V
U
, V
L
, VSd
l
O
I
P
f
O
T
C
T
CS
VALUE
100
18
18
V
LPI
+ 0.5
5
10
50
-55 to +125
-55 to +150
UNITS
V
V
V
V
A
A
kHz
°C
°C
TABLE 2. PWR-82341 SPECIFICATIONS
(TC=+25°C Unless Otherwise Specified)
PARAMETER
OUTPUT
Output Current Continuous
Supply Voltage
Output On-Resistance (each FET)
Instant Forward Voltage (intrinsic diode)
Reverse Recovery Time (intrinsic diode)
Reverse Leakage Current
INPUT POWER
Input Voltage (T
C
=-55°C to +125°C)
Logic Power-in Voltage
V+ Current
Logic Power Input Current
INPUT SIGNALS
Positive Trigger Threshold Voltage
Negative Trigger Threshold Voltage
Positive Trigger Threshold Voltage
Negative Trigger Threshold Voltage
SWITCHING CHARACTERISTICS
(See FIGURE 2)
Upper Drive:
Turn-on Propagation Delay
Turn-off Propagation Delay
Shut-down Propagation Delay (see FIGURE 5)
Turn-on Rise Time
Turn-off Fall Time
Lower Drive:
Turn-on Propagation Delay
Turn-off Propagation Delay
Shut-down Propagation Delay (see FIGURE 5)
Turn-on Rise Time
Turn-off Fall Time
SWITCHING CHARACTERISTICS
(Ssee FIGURE 2)
Upper Drive:
Turn-on Propagation Delay
Turn-off Propagation Delay
Shut-down Propagation Delay (see FIGURE 5)
Turn-on Rise Time
Turn-off Fall Time
SYMBOL
I
o
V
cc
R
ON
V
F
t
rr
I
r
V+
V
LPI
I+
I
LPI
V
P
V
N
V
P
V
N
TEST CONDITIONS
See NOTE 1
Ip=5A (See NOTE 2)
Ip=5A (See NOTE 2)
Id=1A, di
d
/dt=160A/µs
See NOTE 3
MIN
TYP
MAX
5
100
0.13
1.25
500
250
18
18
35
5
10
7
3
2
UNIT
A
V
Ω
V
nsec
µA
V
V
mA
mA
V
V
V
V
28
160
V+ = 15V, f
o
= 20kHz
V
LPI
= 15 V
12
5
15
Pin Connections
V
LPI
= 15 V
V
LPI
= 15 V
V
LPI
= 5 V
V
LPI
= 5 V
6.8
4.0
2.2
0.9
td(on)
td(off)
tsd
tr
tf
Test 1 Conditions
V
LPI
= +15 V, V+ = 15 V
V
CC
= +28 V, I
p
= 10 A
825
1100
1000
125
200
nsec
nsec
nsec
nsec
nsec
td(on)
td(off)
tsd
tr
tf
825
1100
1000
200
200
nsec
nsec
nsec
nsec
nsec
td(on)
td(off)
tsd
tr
tf
Test 2 Conditions
V
LPI
= +5 V, V+ = 15 V
V
CC
= +28 V, I
p
= 10 A
1150
1400
1050
125
225
nsec
nsec
nsec
nsec
nsec
2
PWR-82341 Errata Sheet
This errata sheet replaces the section on INPUT SIGNALS in Table 2 on page 2.
TABLE 2. PWR-82340/82342 SPECIFICATION
(T
C
= +25°C Unless Otherwise Specified)
PARAMETER
INPUT SIGNALS (See Figure 7)
Positive Trigger Threshold Voltage
Negative Trigger Threshold Voltage
Hysteresis Voltage
Positive Trigger Threshold Voltage
Negative Trigger Threshold Voltage
Hysteresis Voltage
SYMBOL
V
P
V
N
V
H
V
P
V
N
V
H
TEST CONDITIONS
Pin Connections
V
LPI
= 15V
V
LPI
= 15V
V
LPI
= 15V
V
LPI
= 5V
V
LPI
= 5V
V
LPI
= 5V
MIN
TYP
MAX
12.9
2.1
1.6
0.9
0.3
10.8
4.3
3.6
UNIT
V
V
V
V
V
V
TABLE 2. PWR-82341 SPECIFICATIONS (continued)
(T
C
= +25°C Unless Otherwise Specified)
PARAMETER
SWITCHING CHARACTERISTICS (continued)
Lower Drive:
Turn-on Propagation Delay
Turn-off Propagation Delay
Shut-down Propagation Delay (see FIGURE 5.)
Turn-on Rise Time
Turn-off Fall Time
DEAD TIME
MINIMUM PULSE WIDTH
THERMAL
Maximum Thermal Resistance
Junction Temperature Range
Case Operating Temperature
Case Storage Temperature
WEIGHT
NOTES:
1. For Hi-Reliability applications, derating per MIL-S-19500 should be observed. (Derate V
CC
to 70%.)
2. Pulse Width
≤
300
µs,
duty cycle
≤
2%
3. V
CC
= 70 V, V
U
, V
L
, = logic ‘0’
SYMBOL
TEST CONDITIONS
Test 2 Conditions
V
LPI
= +5 V, V+ = 15 V
V
CC
= +28 V, I
p
= 10 A
MIN
TYP
MAX
UNITS
td(on)
td(off)
tsd
tr
tf
t
dt
t
pw
θjc
Tj
T
CO
T
CS
1150
1400
1050
125
225
400
150
7.5
150
125
150
1.05
(30)
nsec
nsec
nsec
nsec
nsec
nsec
nsec
°C/W
°C
°C
°C
0z
(g)
each transistor
-55
-55
-55
INTRODUCTION
The PWR-82341 is a 5 Amp, H-bridge motor drive hybrid which
incorporates a 100 Vdc MOSFET output stage for high-speed
and high-efficiency operation. This motor drive is ideal for use in
high-performance motion control systems, servo amplifiers, and
motor speed control designs. Furthermore, Multi-axis systems
requiring multiple drive stages can benefit from the small size of
this power drive.
The PWR-82341 can be driven directly from a PWM, DSP, or a
custom ASIC that supplies digital signals to control the upper
and lower transistors of each phase. This highly integrated drive
stage has Schmitt Trigger digital inputs that control the high and
low side of each phase. Digital protection of each phase elimi-
nates an in-line firing condition, by preventing simultaneous turn-
on of both the upper and lower transistors. This logic also con-
trols the high and low-side gate drivers. Operation from +5 to +15 V logic
levels can be programmed by applying the appropriate voltage
INPUTS:
to the VLpi pin . The PWR-82341 has a ground referenced low-
side gate drive. An internal charge pump circuit supplies the
required drive voltage to the two high-side transistors. This pro-
vides a continuous high-side gate drive; even during motor stall.
The high and low-side gate drivers control the N-channel
MOS-FET output stage. The MOSFETs used in the PWR-82341
allow output switching up to 50 kHz. The PWR-82341 does not
have internal short-circuit or overcurrent protection; which if
required, must be added externally to the hybrid.
DIGITALLY CONTROLLED INPUTS
The PWR-82341 uses Schmitt Trigger digital inputs (with hys-
teresis) to ensure high noise immunity. The trigger switches at
different points for positive and negative going signals.
Hysteresis voltage (V
H
) is the difference between the positive
going voltage (V
P
) and the negative going voltage (V
N
)
(see FIGURE 3).
The digital inputs have programmable logic levels, which allows
the hybrid to be used with different types of control logic with an
input voltage range of +5 to +15 V, such as TTL or CMOS logic.
The Vlpi pin is the logic power input for the digital circuitry inside
the hybrid.
A 0.01 µF, 50 V ceramic capacitor must be placed
between VLpi pin and GND as close to the hybrid as possi-
ble.
When using 5 V control circuitry, an external +5 Vdc power
supply must be connected between the Vlpi pin of the hybrid,
and GND. The control circuitry can be as simple as a PWM, or
as sophisticated as a microprocessor or custom ASIC, depend-
ing on the system requirements. FIGURE 4 illustrates a typical
interface of the PWR-82341 with a motor and PWM in a Servo-
Amp System.
50%
t
r
OUTPUTS:
t
f
90%
50%
10%
t
d
(ON)
t
d
(OFF)
(REFERENCE TABLE 2. ALSO)
FIGURE 2. INPUT/OUTPUT TIMING RELATIONSHIPS
3
SHUT-DOWN INPUT (
V
Sd
)
The V
Sd
pin provides a digital shut-down input, which allows the
user to completely turn off both the upper and lower-output tran-
sistors in all three phases. Application of a logic “1” to the V
Sd
input will latch the Digital Control/Protection circuitry thereby
turning off all output transistors. The Digital Control/Protection
circuitry remains latched in the off state and will not respond to
signals on the V
L
or V
U
inputs while the V
Sd
has a logic “1”
applied. When the user or the sense circuitry (as in FIGURE 6)
returns the V
Sd
input to a logic “0”, and then the user sets the V
L
and V
U
inputs to a logic “0” the output of the Digital
Control/Protection circuitry will clear the internal latch. When the
next rising edge (see FIGURE 5) occurs on the V
L
or V
U
digital
inputs, the outputs transistors will respond to the corresponding
digital input. This feature can be used with external current limit
or temperature sense circuitry to disable the drive if a fault con-
dition occurs (see FIGURE 6).
that the upper and lower transistors of the same phase conduct
together, the output would be a high impedance until removal of
the illegal code from the input of the PWR-82341.
A dead time
of 400 nsec minimum should still be maintained between
the signals at the Vu and VL pins;
this ensures the complete
turn-off of any transistor before turning on its associated in-line
transistor.
TABLE 3. INPUT-OUTPUT TRUTH TABLE
INPUTS
OUTPUTS
UPPERS
V
UA
0
0
1
1
X
0
x
V
UB
0
1
1
X
1
0
x
LOWERS
V
LA
1
1
0
1
X
0
x
V
LB
1
0
0
X
1
0
x
L = Low Level
Z = High Impedance State (off)
CONTROL
V
SD
0
0
0
0
0
0
1
V
OA
L
L
H
Z
X
z
z
V
OB
L
H
H
X
Z
z
z
INTERNAL PROTECTION CIRCUITRY
The hybrid contains digital protection circuitry, which prevents in-
line transistors from conducting simultaneously. This, in effect,
would short circuit the power supply and would damage the out-
put stage of the hybrid. This circuit permits only proper input sig-
nal patterns to produce output conduction. TABLE 3 lists the
input/output timing relationships. If an improper input requested
H = High Level
X = Don’t Care
1
2
V
v
V
H
V
O
N
v
p
FIGURE 3. HYSTERESIS DEFINITION AND CHARACTERISTICS
+ 28 V
+ 15 V
+ +CAP
-
CAP
V+
GND
V
LPI
V
UA
V
LA
CHARGE PUMP
V
CC
V
OA
DRIVE
A
POSITION
COMMAND
POSITION
LOOP
AND
PWM
V
UB
V
LB
V
Sd
DIGITAL
CONTROL
AND
PROTECTION
CIRCUITRY
DRIVE
B
V
SS
V
CC
MOTOR
+
TANT
V
OB
V
SS
PWR-82341
FIGURE 4. TYPICAL INTERFACE WITH A MOTOR AND PWM
4
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