M50LPW041
4 Mbit (512Kb x8, Uniform Block)
3V Supply Low Pin Count Flash Memory
PRELIMINARY DATA
s
SUPPLY VOLTAGE
– V
CC
= 3V to 3.6V for Program, Erase and
Read Operations
– V
PP
= 12V for Fast Program and Fast Erase
s
LOW PIN COUNT (LPC)
– Standard Interface for embedded operation
with PC Chipsets that are without automap-
ping memory features
PLCC32 (K)
s
ADDRESS/ADDRESS MULTIPLEXED
– A/A Mux Interface for programming equip-
ment compatibility
s
LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block Pro-
tection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for plat-
form design flexibility
– Synchronized with 33MHz PCI clock
4
ID0-ID3
5
GPI0-
GPI4
LFRAME
CLK
IC
RP
INIT
TSOP40 (N)
10 x 20mm
Figure 1. Logic Diagram (LPC Interface)
VCC VPP
4
LAD0-
LAD3
WP
TBL
s
BYTE PROGRAMMING TIME
– Single Byte Mode: 10µs (typical)
– Quadruple Byte Mode: 2.5µs (typical)
s
s
8 UNIFORM 64 Kbyte MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
M50LPW041
s
PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase Suspend
s
s
FOR USE in PC BIOS APPLICATIONS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 3Ch
VSS
AI05785
September 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/37
M50LPW041
Figure 2. Logic Diagram (A/A Mux Interface)
DESCRIPTION
The M50LPW041 is a 4 Mbit (512Kb x8) non-
volatile memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
VCC VPP
11
A0-A10
8
DQ0-DQ7
RC
IC
G
W
RP
M50LPW041
RB
VSS
AI05786
Figure 3. PLCC Connections
A/A Mux
A8
A9
RP
VPP
VCC
RC
A10
A/A Mux
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
GPI1
GPI0
WP
TBL
ID3
ID2
ID1
ID0
LAD0
GPI2
GPI3
RP
VPP
VCC
CLK
GPI4
1 32
IC (VIL)
NC
NC
VSS
VCC
INIT
LFRAME
RFU
RFU
IC (VIH)
NC
NC
VSS
VCC
G
W
RB
DQ7
9
M50LPW041
25
17
LAD1
LAD2
VSS
LAD3
RFU
RFU
RFU
A/A Mux
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
A/A Mux
AI05788
Note: Pins 27 and 28 are not internally connected.
2/37
M50LPW041
Figure 4. TSOP Connections
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
VCC
VPP
RP
NC
NC
A9
A8
A7
A6
A5
A4
NC
IC (VIL)
NC
NC
NC
NC
GPI4
NC
CLK
VCC
VPP
RP
NC
NC
GPI3
GPI2
GPI1
GPI0
WP
TBL
1
40
10
31
M50LPW041
11
30
20
21
VSS
VCC
LFRAME
INIT
RFU
RFU
RFU
RFU
RFU
VCC
VSS
VSS
LAD3
LAD2
LAD1
LAD0
ID0
ID1
ID2
ID3
VSS
VCC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A/A Mux
A/A Mux
AI06872
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW041 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in a PLCC32 or TSOP40
(10mm x 20mm) package and is supplied with all
the bits erased (set to 1).
System Memory Mapping
The LPC address sequence is 32 bits long. The
M50LPW041 responds to addresses mapped to
the top of the 4 GByte memory space, from
FFFF FFFFh. Address bits A31-A24 must be set
to 1. A23 is set to 1 for array access, and to 0 for
register access.
The M50LPW041 also responds to addresses
mapped to the bottom of the 4 GByte memory
space, from 0000 0000h. Address bits A31-A24
must be set to 0. A23 is set to 0 for array access,
and to 1 for register access.
For A22-A19, see Table 2. A18-A0 are for array
addresses.
Table 1. Signal Names (LPC Interface) Memory
LAD0-LAD3
LFRAME
ID0-ID3
GPI0-GPI4
IC
RP
INIT
CLK
TBL
WP
RFU
V
CC
V
PP
V
SS
NC
Input/Output Communications
Input Communication Frame
Identification Inputs
General Purpose Inputs
Interface Configuration
Interface Reset
CPU Reset
Clock
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected or set at V
IL
or V
IH
.
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Not Connected Internally
3/37
M50LPW041
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Input/Output Communications (LAD0-LAD3).
All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (LFRAME).
The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
nication Frame is Low, V
IL
, on the rising edge of
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
IL
, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, V
IH
, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3).
The Identification
Inputs (ID0-ID3) allow to address up to 16
memories on a bus. The value on addresses A19-
A22 is compared to the hardware strapping on the
ID0-ID3 pins to select which memory is being
addressed, as shown in Table 2.
General Purpose Inputs (GPI0-GPI4).
The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
be left to float, they should be driven Low, V
IL,
or
High, V
IH
.
Interface Configuration (IC).
The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
Table 2. Memory Identification Input Configuration
Top
Memory
Number
1 (Boot)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ID2
ID2
ID1
ID0
A
22
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A
21
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A
20
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A
19
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A
22
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bottom
A
21
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
20
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
19
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
IL
or floating V
IL
or floating V
IL
or floating V
IL
or floating
V
IL
or floating V
IL
or floating V
IL
or floating
V
IL
or floating V
IL
or floating
V
IL
or floating V
IL
or floating
V
IL
or floating
V
IL
or floating
V
IL
or floating
V
IL
or floating
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
or floating
V
IH
V
IL
or floating V
IL
or floating
V
IL
or floating
V
IH
V
IH
V
IH
V
IL
or floating
V
IH
V
IL
or floating V
IL
or floating V
IL
or floating
V
IL
or floating V
IL
or floating
V
IL
or floating
V
IL
or floating
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
or floating
V
IH
V
IL
or floating V
IL
or floating
V
IL
or floating
V
IH
V
IH
V
IH
V
IL
or floating
V
IH
4/37
M50LPW041
Table 3. System Memory Map
A31:24
Array
Top
Bottom
FFh
00h
1
0
A23
Register
0
1
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, V
IL
; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
IH
. An internal pull-down resistor is
included with a value of R
IL
; there will be a leakage
current of I
LI2
through each pin when pulled to V
IH
;
see Table 21.
Interface Reset (RP).
The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
IL
, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
IH
, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT).
The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK).
The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL).
The Top Block Lock
input is used to prevent the Top Block (Block 7)
from being changed. When Top Block Lock, TBL,
is set Low, V
IL
, Program and Block Erase
operations in the Top Block have no effect,
regardless of the state of the Lock Register. When
Top Block Lock, TBL, is set High, V
IH
, the
protection of the Block is determined by the Lock
Register. The state of Top Block Lock, TBL, does
not affect the protection of the Main Blocks (Blocks
0 to 6).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
Write Protect (WP).
The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
set Low, V
IL
, Program and Block Erase operations
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
WP, is set High, V
IH
, the protection of the Block is
determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 7).
Write Protect, WP, must be set prior to a Program
or Block Erase operation is initiated and must not
be changed until the operation completes or un-
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
WP during Program or Erase Suspend.
Reserved for Future Use (RFU).
These pins do
not have assigned functions in this revision of the
part. They may be left disconnected or driven Low,
V
IL
, or High, V
IH
.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2, Logic Diagram, and Table
4, Signal Names.
Address Inputs (A0-A10).
The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A18). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC).
The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row
Address bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column
Address bits are latched on the rising edge.
Ready/Busy Output (RB).
The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, V
OL
, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase
Suspend command. When Ready/Busy is High,
V
OH
, the memory is ready for any Read, Program
or Erase operation.
5/37
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