SN54F374, SN74F374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDFS077A – D2932, MARCH 1987 – REVISED OCTOBER 1993
•
•
•
•
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Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Package Options Include Plastic
Small-Outline (SOIC) and Shrink
Small-Outline (SSOP) Packages, Ceramic
Chip Carriers, and Plastic and Ceramic
DIPs
SN54F374 . . . J PACKAGE
SN74F374 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the
′F374
are edge-triggered
D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic
levels that were set up at the data (D) inputs.
A buffered output enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
2D
2Q
3Q
3D
4D
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54F374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
The output enable (OE) input does not affect internal operations of the flip-flop. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74F374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F374 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74F374 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
Copyright
©
1993, Texas Instruments Incorporated
2–1
SN54F374, SN74F374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDFS077A – D2932, MARCH 1987 – REVISED OCTOBER 1993
logic symbol
†
OE
CLK
1
11
EN
C1
2
5
6
9
12
15
16
19
logic diagram (positive logic)
OE
CLK
1D
1
11
C1
3
2
1Q
1D
2D
3D
4D
5D
6D
7D
8D
3
4
7
8
13
14
17
18
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
To Seven Other Channels
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
CC
Current into any output in the low state: SN54F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
SN74F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Operating free-air temperature range: SN54F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F374
MIN
VCC
VIH
VIL
IIK
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature
– 55
4.5
2
0.8
– 18
–3
20
125
0
NOM
5
MAX
5.5
SN74F374
MIN
4.5
2
0.8
– 18
–3
24
70
NOM
5
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
2–2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54F374, SN74F374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDFS077A – D2932, MARCH 1987 – REVISED OCTOBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 4.5 V,
VCC = 4 5 V
4.5
VCC = 4.75 V,
VOL
IOZH
IOZL
II
IIH
IIL
IOS‡
VCC = 4 5 V
4.5
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
TEST CONDITIONS
II = – 18 mA
IOH = – 1 mA
IOH = – 3 mA
IOH = – 1 mA to – 3 mA
IOL = 20 mA
IOL = 24 mA
VO = 2.7 V
VO = 0.5 V
VI = 7 V
VI = 2.7 V
VI = 0.5 V
VO = 0
– 60
SN54F374
MIN TYP†
MAX
– 1.2
2.5
2.4
3.4
3.3
0.3
0.5
0.35
50
– 50
0.1
20
– 0.6
–150
– 60
0.5
50
– 50
0.1
20
– 0.6
–150
86
2.5
2.4
2.7
V
µA
µA
mA
µA
mA
mA
mA
3.4
3.3
V
SN74F374
MIN TYP†
MAX
– 1.2
UNIT
V
ICCZ
VCC = 5.5 V,
See Note 2
55
86
55
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICCZ is measured with OE at 4.5 V and all other inputs grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
′F374
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration
CLK high
CLK low
High
Setup time, data before CLK↑
time
Hold time data after CLK↑
time,
Low
High
Low
0
7
6
2
2
2
2
MAX
100
MIN
0
7
6
2.5
2
2
2.5
MAX
60
MIN
0
7
6
2
2
2
2
MAX
70
MHz
ns
SN54F374
SN74F374
UNIT
ns
ns
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2–3
SN54F374, SN74F374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDFS077A – D2932, MARCH 1987 – REVISED OCTOBER 1993
switching characteristics (see Note 3)
VCC = 5 V,
CL = 50 pF,
RL = 500
Ω,
TA = 25°C
′F374
MIN
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
100
CLK
Q
Q
Q
3.2
3.2
1.2
1.2
1.2
6.1
6.1
8.6
5.4
4.9
8.5
8.5
11.5
7.5
7
TYP
MAX
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
Ω,
TA = MIN to MAX†
SN54F374
MIN
60
3.2
3.2
1.2
1.2
1.2
10.5
11
14
10
8
MAX
SN74F374
MIN
70
3.2
3.2
1.2
1.2
1.2
10
10
12.5
8.5
8
6.5
MAX
MHz
ns
ns
ns
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
OE
OE
tPLZ
1.2
3.9
5.5
1.2
7.5
1.2
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
2–4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright
©
1998, Texas Instruments Incorporated
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