Data Sheet
PT7C4050
PLL with Integrated VCXO
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Features
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PLL with quartz stabilized VCXO
Crystal output jitter less than 25ps
Dual redundant reference input clocks with loss of
signal detection
Manual or automatic switch over between reference
input clocks
VCXO provides smooth output transition during
switch over of input clocks
Lock detection
Selectable metal mask options for phase detectors,
op. Amps, and charge pump
Loss of signals alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 40 Mb/s
Tri-state output
User defined PLL loop response
NRZ data compatible
Crystal frequency range: 16.0000 to 42.0000MHz
Supply voltage: 3.0~5.5V
Description
The device is composed of phase-lock loop with
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported: 16.000~42.000MHz.
Ordering Information
Part Number
PT7C4050DE
PT7C4050LE
Package
Die form
Lead free 28-Pin TSSOP
Applications
•
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•
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Frequency translation
Clock Smoothing, Clock Switching
NRZ Clock Recovery
Optical Switching/Routing, Base Station
Crystal frequency description
Part No
Crystal frequency used (MHz)
16.384
19.440
20.000
24.704
PT7C4050
25.000
32.768
34.368
38.880
40.960
PT0239L (10/08)
1
Ver: 1
Data Sheet
PT7C4050
PLL with Integrated VCXO
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Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
Loss Of Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPOUT
OPN
OPP
Op
Amp
Pin Configuration
PT0239L (10/08)
2
Ver: 1
Data Sheet
PT7C4050
PLL with Integrated VCXO
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Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
*1
21
22
23
*2
24
25
26
27
28
X1
VC
NC
AGND
OPN
OPOUT
OPP
S1
S2
S3
LOS-IN1
(LOSIN)
PHO
REF-CLK1
(DATAIN)
FB-CLK
(CLKIN)
DGND
LOS
RCLK
(CLK-OUT3)
RDATA
(CLK-OUT4)
DVDD
CLK-OUT2
HIZ
CLK-OUT1
SEL-OUT1
GND
AVDD
(XT-VDD)
NC
NC
X2
S1, S2, S3 Options for selectable divider N
TTL input.
Internal pull down. Normally this pin is connected to OUT1 and selects REF-CLK1
input
Output.
signal produced by phase detector of data.
Input clock signal.
to phase detector
(TTL switching thresholds for recovering DATAIN)
TTL switching thresholds input.
Connected to external feedback clock.
Digital ground.
Loss of signal detection.
for DATAIN input. Refer to LOS detection description.
Output recovered clock.
Output recovered data stream.
Digital power supply.
Output clock
of internal VCXO frequency controlled by S3, S2, S1 while S4 set logic high
TTL input.
When set to a logic low, output pins CLK-OUT1, CLK-OUT2, RCLK, and RDATA
buffers are set to high-impedance state. When set to logic high or no connection, the device
functions and output pins CLK-OUT1, CLK-OUT2, RCLK, and RDATA etc. are active. This input
has an internal pull-up resistor.
Output clock.
of internal VCXO or half VCXO frequency, controlled by SEL-OUT1.
CMOS input.
‘LO’ selects half of internal VCO frequency. ‘HI’ selects internal VCO frequency.
Internal pull up.
Ground.
Analog power supply.
Not connected.
Not connected.
Crystal oscillator connected between X1 and X2
Sym
Description
Crystal oscillator connected between X1 and X2
Control voltage input.
It controls crystal oscillator (VCXO).
Not connected.
Analog ground.
Negative input.
terminal to internal operational amplifier.
Output.
terminal of internal operational amplifier.
Positive input.
terminal to internal operational amplifier.
Note:
*
1
: S3, S2, S1 option for selectable divider N, Please refer to Table 1
*
2
: SEL-OUT1 option for VCXO or half VCXO output freq. Please refer to Table 2
( ): For pin11/13/14/17/18/25, die option
PT0239L (10/08)
3
Ver: 1
Data Sheet
PT7C4050
PLL with Integrated VCXO
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Pad Location
X1-2
X1-1
X2-2
X2-1
IFr
VC
AGND1
AGND2
NC1
OPN
LF
REF-indica tor1
REF-indica tor2
OPOUT
REF-SEL
NC2
OPP
CTRL-SEL
Ala rm-re s
NC3
S0
S1
S2
S3
S4
REF-CLK1(Da tain)
FB-CLK(Clkin)
AVDD
XT-VDD
XT-GND
GND(CDL)
SEL-OUT1
CLK-OUT1
NC9
NC8
PT7C4050
HIZ
LD
NC7
CLK-OUT2
NC6
Sel_050
DVDD2
DVDD1
RDATA(CLK-OUT 4)
RCLK(CLK-OUT3)
LOS-OUT2
LOS-OUT1
LOS*
LOS-IN1(LOSIN)
Die size: 2190×3401µm(Including scribe line).
Die thickness: 300µm(no coating).
Table 1 Bonding Options for selectable divider N
S3
S2
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
Table 2 Bonding Options for CLK-OUT1
SEL-OUT1
1
0
S1
1
0
1
0
1
0
1
0
Divider N
2
4
8
16
32
64
128
256
CLK-OUT1 frequency
Internal VCXO frequency
Half of internal VCXO frequency
PT0239L (10/08)
4
REF-CLK2
PHO
NC4
NC5
DGND1
LOS-IN2
DGND2
Ver: 1
Data Sheet
PT7C4050
PLL with Integrated VCXO
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Function Description
LOS detection
LOS-OUT1 provides output alarm flag when REF-CLK1 is lost. The LOS output is set to logic high after 256 consecutive
FB-CLK (CLKIN) periods with no REF-CLK1 (DATAIN) transitions. As soon as a transition occurs at REF-CLK1 (DATAIN),
LOS is reset to a logic low.
Divider output signals
The internal divider N is 2,4,8, ------, 8192, and creates 5 kinds of 8KHZ frame signals: F0N, F8, F16N, RSP, TSP. F0N
outputs to CLK-OUT3 pin, F16N outputs to CLK-OUT4 pin. The F8, TSP, RSP can be selected by S4:1 (bond option) and output
to CLK-OUT2 pin.
8KHZ frame signals’ generator based on 32MHZ VCXO frequency. All signals are compatible with 4409 DPLL product.
PT0239L (10/08)
5
Ver: 1
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