SD-14595/96/97
SYNCHRO/RESOLVER-TO-DIGITAL
CONVERTERS
DESCRIPTION
The SD-14595 is a low-cost, high
reliability, synchro- or resolver-to-dig-
ital converter with 14-bit-only, 16-bit-
only or pin programmable 14-bit or
16-bit resolution. Packaged in a 36-
pin DDIP, the SD-14595/96/97 series
feature Built-In-Test (BIT) output.
The SD-14595/96/97 series accepts
broadband inputs: 360 to 1 kHz. Other
features are solid-state signal and ref-
erence isolation and high common
mode rejection. In addition, the SD-
14596 and SD-14597 are pin-for-pin
replacements for the Natel 1044 and
1046, respectively.
The digital angle output from the
SD-14595/96/97 is a natural binary
code, parallel positive logic and is
TTL/CMOS compatible. The SD-
14595/96/97 accomplishes synchro-
nization to a computer with the
Converter Busy (CB) output and/or the
Inhibit (INH) input.
FEATURES
•
Single +5 V Power Supply
•
Accuracy to 1.3 Arc Minutes
•
Pin Programmable 14 Bit/16 Bit,
14 Bit Only or 16 Bit Only
APPLICATIONS
Because of its high reliability, small
size, and low power consumption, the
SD-14595/96/97 is ideal for military
ground or avionics applications. All
models are available with MIL-PRF-
38534 processing.
Designed with three-state output, the
SD-14595/96/97 is especially well-
suited for use with computer based
systems. Among the many possible
applications are radar and navigation
systems, fire control systems, flight
instrumentation, and flight trainers or
simulators.
SOLID STATE RESOLVER INPUT OPTION
•
No 180° False Lock-up
•
Internal Synthesized Reference
•
Built-In-Test (BIT) Output
•
Low Power
•
Pin-for-Pin Replacement for
Natel’s 1044 and 1046
SOLID STATE SYNCHRO INPUT OPTION
DIRECT INPUT OPTION
SIN
θ
COS
θ
VOLTAGE
FOLLOWER
BUFFER
SIN
θ
COS
θ
INTERNAL
DC
REFERENCE
S1
S2
S3
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
S4
RESOLVER
CONDITIONER
SIN
θ
COS
θ
INPUT OPTIONS
RH
V
REF IN
RL
BIT
REFERENCE
CONDITIONER
R
SYNTHESIZED
REF
LOS
SIN
θ
INPUT OPTION
COS
θ
LOS
e
BIT DETECT
VEL
HIGH
ACCURACY
CONTROL
TRANSFORMER
GAIN
e
SIN
(θ-φ)
DEMODULATOR
D
VEL
ERROR
PROCESSOR
T
VCO
U
E
1 LSB ANTIJITTER FEEDBACK
16 BIT CT
TRANSPARENT
LATCH
U
16 BIT
UP/DOWN
COUNTER
T
INH
CB
DIGITAL
ANGLE
φ
50 ns DELAY
Q
INHIBIT
TRANSPARENT
LATCH
INH
3 STATE
TTL BUFFER
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
T
EDGE
TRIGGERED
LATCH
V
14B
RESOLUTION (14595 ONLY)
CONTROL
+8.6 V
ANALOG RETURN
V(+4.3 V)
VOLTAGE
DOUBLER
+5 V
HBE
BITS 1-8
BITS 9-16 LBE
FIGURE 1. SD-14595/96/97 BLOCK DIAGRAM
©
1997, 1999 Data Device Corporation
SD-14595/96/97 SPECIFICATIONS
Specifications apply over temperature range, power supply range, ref-
erence frequency, and amplitude range; 15% signal amplitude varia-
tion, up to 10% harmonic distortion in the reference, and up to 45° of
signal to reference phase shift.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILTY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Range
Voltage Range
Hz
47-1000 (60 Hz Unit)
Hz
360-1000 (400 Hz Unit)
Vrms 4-130 (for 11.8 Vor 90 V sig-
nal input)
3-100 (for 1 V direct signal input)
UNIT
Bits
Min
LSB
VALUE
14 or 16
5.2, 2.6, or 1.3
1 Max
TABLE 1. SD-14595/96/97 SPECIFICATIONS (CONT)
PARAMETER
DIGITAL INPUT/OUTPUT
(cont)
Resolution Control (14B)
(for Programmable Units Only)
UNIT
VALUE
Enable Bits 1 to 8 (HBE)
Enable Bits 9 to 16 (LBE)
(9 to 14 for 14-bit mode)
Logic 1 for 14 bits
Logic 0 for 16 Bits
Pull-up current source to
+5 V//5 pF max CMOS
transient protected
Logic 0 enables
Data Valid within 150 ns
Logic 1 = High Z
Data High Z within 100 ns
Pull-down current source
to GND//5 pF max CMOS
transient protected
Outputs:
Parallel Data
Bits
14 or 16 parallel lines;
natural binary angles, posi-
tive logic (see TABLE 3)
0.8 to 3.0 µs positive pulse;
leading edge initiates
counter update.
Logic 1 for fault conditions.
50 pF + rated logic drive
Logic 0; 1 TTL load,
1.6 mA at 0.4 V max
Logic 1; 10 TTL loads,
0.4 mA at 2.8 V min High
Z;10 µA//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply
minus 100 mV min
driving CMOS
Input Impedance:
n
Single Ended
n
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance)
Input Impedance Imbalance
n
Synchro
• Zin Line-to-Line
• Zin Each Line-to-Gnd
• Common Mode Range
• Maximum Transient Peak
Voltage
n
Resolver
• Zin Single Ended
• Zin Differential
• Zin Each Line-to Gnd
• Common Mode Range
• Maximum Transient Peak
Voltage
n
Direct (1.0 V L-L)
• Input Signal Type
Ohm
Ohm
V
250k min
500k min
250 peak max
Converter Busy (CB)
BIT
Drive Capability
%
V
Ohm
Ohm
Vpeak
V
V
Ohm
Ohm
Ohm
V
V
0.2 max
11.8 V L-L 90 V L-L
17.5k
130k
11.5k
85k
30
180
150
11.8 V L-L
23k
46k
23k
60 max
150
• Sin/Cos Voltage Range
• Max Voltage w/o Damage
• Input Impedance
REFERENCE SYNTHESIZER
± Sig/Ref Phase Shift
DIGITAL INPUT/OUTPUT
Logic Type
Inputs:
Vrms
Ohm
Sin and Cos resolver sig-
nals referenced to converter
internal DC reference V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M // 10 pf voltage
follower
60 typ, 45 guaranteed
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 µA max
Logic 0 inhibits Data stable
within 0.5 µs (pull up)
ANALOG OUTPUT
Analog Return (V)
Velocity (VEL) (See note 3.)
AC error (e)
n
14-Bit Mode
n
16-Bit Mode
Load
DYNAMIC CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Tolerance
Max Voltage w/o Damage
Current
TEMPERATURE
RANGES
Operating (-1XX or -4XX)
(-3XX or -8XX)
Storage
PHYSICAL CHARACTERISTICS
+4.3 V nom
See TABLE 4.
mV
rms
3.5 per LSB of error
mV
rms
1.75 per LSB of error
mA 1
See TABLE 6
V
%
V
mA
+5
±10
+7
25 max+digital output load
Deg
°C
°C
°C
-55 to +125
0 to 70
-65 to +150
Inhibit (INH)
in
.9 x 0.78 x 0.21
(mm) (48 x 20 x 5.3 )
36-Pin Double Dip
oz(g) 0.7 max (20)
2
TABLE 1. SD-14595/96/97 SPECIFICATIONS (CONTD)
PARAMETER
TRANSFORMER
CHARACTERISTICS
(See ordering information for list
of Transformers.
Reference Transformers are
Optional for Both Solid-State
and Voltage Follower Input
Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
Signal Transformer
Carrier Frequency Range
Breakdown Voltage to GND
Minimum Input impedances
(Balanced)
90 V L-L
26 V L-L
11.8 V L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
VALUE
THEORY OF OPERATION
The SD-14595/96/97 series are small, 36-pin DDIP synchro-to-
digital hybrid converters. As shown in the block diagram (FIG-
URE 1), the SD-14595/96/97 can be broken down into the fol-
lowing functional parts: Signal Input Option, Converter, Analog
Conditioner, Power Supply Conditioner, and Digital Interface.
CONVERTER OPERATION
As shown in FIGURE 1, the converter section of the SD-
14595/96/97 contains a high accuracy control transformer,
demodulator, error processor, voltage controlled oscillator
(VCO), up-down counter, and reference conditioner. The con-
verter produces a digital angle which tracks the analog input
angle to within the specified accuracy of the converter.The con-
trol transformer performs the following trigonometric computa-
tion:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
SynchroZ
IN
(Z
SO
)
180
Ω
-
20 kΩ
ResolverZ
IN
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
360-1000 Hz
700 V peak
Where:
100 kΩ
30 kΩ
30 kΩ
θ
is angle theta representing the resolver shaft position.
φ
is digital angle phi contained in the up/down counter.
The tracking process consists of continually adjusting
φ
to make
(θ -
φ)
= 0, so that
φ
will represent the shaft position
θ.
The output of the demodulator is an analog dc level proportional
to sin(θ -
φ).
The error processor receives its input from the
demodulator and integrates this sin(θ -
φ)
error signal which then
drives the VCO. The VCO’s clock pulses are accumulated by the
up/down counter. The velocity voltage accuracy, linearity and off-
set are determined by the quality of the VCO. Functionally, the
up/down counter is an incremental integrator. Therefore, there
are two stages of integration which makes the converter a Type
II tracking servo.
In a Type II servo, the VCO always settles to a counting rate
which makes dφ/dt equal to dθ/dt without lag. The output data will
always be fresh and available as long as the maximum tracking
rate of the converter is not exceeded.
The reference conditioner is a comparator that produces the
square wave reference voltage which drives the demodulator. It’s
single ended Input Z is 250k ohms/min, 500k ohms differential.
47 - 440 Hz
80 -138 V rms; 115 V rms
nominal resistive
600 kΩ min, resistive
500 V rms transformer isolated
+R (in phase with RH-RL) and -R
(in phase with RL- RH) derived
from op-amps. Short-Circuit proof.
3.0 V nominal riding on ground
reference V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
47 - 440 Hz
10 -100 V rms L- L; 90 V rms
L- L nominal
148 kΩ min L- L balanced
resistive
±500 V rms, transformer isolated
Resolver output,
- sine (- S) + Cosine (+C) derived
from op-amps. Short circuit proof.
1.0 V rms nominal riding on
ground reference V. Output voltage
level tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
Output Voltage
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
Output Voltage
SPECIAL FUNCTIONS
REFERENCE SYNTHESIZER-QUADRATURE VOLTAGES.
The synthesized reference section of the SD-14595 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals typically lead the refer-
ence signal (RH and RL) by about 6°. When an uncompensated
reference signal is used to demodulate the control transformer’s
output, quadrature voltages are not completely eliminated. In a
14-bit converter it is not necessary to compensate for the refer-
ence signal’s phase shift. A 6° phase shift will, however, cause
problems for the one minute accuracy converters. As shown in
FIGURE 1, the converter synthesizes its own cos(ωt +
α)
refer-
Power Required
Notes:
(1) Pin Programmable.
(2) See TABLE 7.
(3) VEL polarity is negative volltage for positive angular rate
3
ence signal from the sinθ - cos(ωt +
α),
cosθ - cos(ωt +
α)
signal
inputs and from the cosωt reference input. The phase angle of
the synthesized reference is determined by the signal input. The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
phase with the signal input, and quadrature errors will therefore
be eliminated.
The synthesized reference circuit also elimi-
nates the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/Full Scale (FS).signal) • tan(α)
Where:
Magnitude of Error is in radians.
Quadrature Voltage is in volts.
Full Scale signal is in volts.
α
= signal to REF phase shift
An example of the magnitude of error is as follows:
Let:
Quadrature Voltage = 11.8 mV
Let:
FS signal = 11.8 V
Let:
α
= 6°
Then: Magnitude of Error = 0.35 min
≅
1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed volt-
age which is determined by the following formula:
Speed Voltage=(rotational speed/carrier frequency) • FS signal
Where:
Speed Voltage is the quadrature due to rotation.
Rotational speed is the rps (rotations per second) of the
synchro or resolver.
Carrier frequency is the REF in Hz.
BIT will also be set for a Loss-of-Signal (LOS) and/or a Loss-of-
Reference (LOR).
PROGRAMMABLE RESOLUTION (14B, PIN 16)
Resolution is controlled by one logic input,14B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
insure that a race condition does not exist between counting and
changing the resolution, input 14B is latched internally on the
trailing edge of CB (see FIGURE 2).
Note: The SD-14595 has programmable resolution whereas the
SD-14596 and 97 do not.
INTERFACING - INPUTS
SIGNAL INPUT OPTIONS
The SD-14595/96/97 series offers direct synchro or resolver
inputs. In a synchro or resolver, shaft angle data is transmitted as
the ratio of carrier amplitudes across the input terminals.
Synchro signals, which are of the form sinθcosωt, sin(θ+120°)
cosωt, and sin(θ+240°)cosωt are internally converted to resolver
format, sinθcosωt and cosθcosωt.
FIGURE 3 illustrates synchro and resolver signals as a function
of the angle
θ.
The solid-state signal and reference inputs are true differential
inputs with high ac and dc common mode rejection.
Input imped-
ance is maintained with power off.
S1-S3 = V
MAX
SINθ
+V
MAX
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
BUILT-IN-TEST (BIT, PIN 15)
The Built-In-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero. If it exceeds approxi-
mately 180 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 0 to logic 1. This condition will occur
during a large step and reset after the converter settles out. BIT
will also change to logic 1 for an over-velocity condition, because
the converter loop cannot maintain input-output and/or if the con-
verter malfunctions where it cannot maintain the loop at a null.
-V
MAX
S3-S2 = V
S2-S1 = V
MAX
SIN(θ
+ 120°)
MAX
SIN(θ
+ 240°)
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
S2-S4 = V
MAX
COS
θ
+V
MAX
In Phase with
RH-RL of Converter
and R2-R4 of RX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
CB
14B
FIGURE 2. RESOLUTION CONTROL TIMING DIAGRAM
4
,,, ,,
0
µs
MIN
0.1
µs
MIN
-V
MAX
S1-S3 = V
MAX
SIN(θ)
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 3. SYNCHRO AND RESOLVER SIGNALS
SOLID-STATE BUFFER INPUT PROTECTION — TRANSIENT
VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high ac and dc common rejection, so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The recurrent ac peak +
dc common mode voltage should not exceed the values in
TABLE 2.
TABLE 2.
INPUT
11.8 VL-L
90 VL-L
Reference
1 VL-L
COMMON MODE
MAXIMUM
30 V Peak
180 V Peak
250 V Peak
MAX TRANSIENT PEAK
VOLTAGE
150 V
150 V
150 V
100 V
90 V line-to-line systems may have voltage transients which
exceed the 500 V specification listed.
These transients can
destroy the thin-film input resistor network in the hybrid.
Therefore, 90 V L-L solid-state input modules may be protected
by installing voltage suppressors as shown. Voltage transients
are likely to occur whenever synchro or resolver are switched on
and off. For instance a 1000 V transient can be generated when
the primary of a CX or TX driving a synchro or resolver input is
opened. See FIGURE 6.
INTERFACING - DIGITAL OUTPUTS AND CONTROLS
DIGITAL INTERFACE
The digital interface circuitry performs three main functions:
1. Latches the output bits during an Inhibit (INH) command allow-
ing stable data to be read out of the SD-14595/96/97.
2. Furnishes parallel tri-state data formats.
REFERENCE
OSCILLATOR
LO
HI
SD-14595/96/97
CB (COUNT)
3. Acts as a buffer between the internal CMOS logic and the
external TTL logic.
In the SD-14595/96/97, applying an Inhibit (INH) command will
lock the data in the inhibit transparent latch without interfering
with the continuous tracking of the converter’s feedback loop.
Therefore the digital angle
φ
is always updated and the INH can
be applied for an arbitrary amount of time. The Inhibit
Transparent Latch and the 50 ns delay are part of the inhibit cir-
cuitry. For further information see the INHIBIT (INH, PIN 13)
paragraph.
RH
RL
VEL (VELOCITY)
R2
R1
S3
S1
S2
STATOR
S3
S1
S2
S4
ROTOR
INH (INHIBIT)
PARALLEL
DATA
FOR 90 V SYNCHRO INPUTS
LBE
HBE
FIGURE 4. SYNCHRO INPUT CONNECTION DIAGRAM
S1
REFERENCE
OSCILLATOR
LO
HI
RD-14595/96/97
CB (COUNT)
CR1
S3
S3
RH
CR3
HYBRID
S2
RL
S1
1N6071A
CR2
S2
RH
RL
CR1, CR2, and CR3 are 1N6136A, bipolar transient voltage suppressors
or equivalent.
FOR 90 V RESOLVER INPUTS
VEL (VELOCITY)
R4
R2
S3
S1
S2
S4
S1
S2
S1
S2
CR4
CR5
S3
S4
HYBRID
S3
S1
S2
S4
PARALLEL
DATA
INH (INHIBIT)
90 V L-L
RESOLVER
INPUT
S3
S4
STATOR
ROTOR
CR4 and CR5 are 1N6136A, bipolar transient voltage suppressors or equivalent.
LBE
HBE
FIGURE 5. RESOLVER INPUT CONNECTION DIAGRAM
5
FIGURE 6. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
FPGA/CPLD
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