64Mx64 bits
Unbuffered DDR SO-DIMM
HYMD264M646B(L)F8-J/M/K/H/L
Document Title
64M x 64 bits Unbuffered DDR SO-DIMM
Revision History
No.
0.1
0.2
Defined Preliminary Specification
1) Defined Pin Cap. Spec.
2) Reflected a "notational" change in module thickness on page 16 - Not Real ! -
3) Corrected some typos
History
Draft Date
Oct. 2003
April 2004
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004
1
64Mx64 bits
Unbuffered DDR SO-DIMM
HYMD264M646B(L)F8-J/M/K/H/L
DESCRIPTION
Hynix HYMD264M646B(L)F8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix
HYMD264M646B(L)F8-J/M/K/H/L series consists of sixteen 32Mx8 DDR SDRAM in FBGA packages on a 200pin
glass-epoxy substrate. Hynix HYMD264M646B(L)F8-J/M/K/H/L series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD232M646B(L)F8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchro-
nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD264M646B(L)F8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
•
•
•
•
200-pin small outline dual in-line memory module
(SO-DIMM)
2.6V +/- 0.1V VDD and VDDQ Power supply
Double data rate architecture; two data accesses per
clock cycle
Differential Clock inputs (CK & /CK)
Data inputs on DQS centers when write
(centered DQ)
•
•
•
•
•
Bidirectional data strobes synchronized with output
data for read and input data for write
Programmable CAS Latency 3 (clock) for DDR400,
2.5(clock) for DDR333
Programmable Burst Length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed RAS
Auto & Self refresh mode
; 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD264M646B(L)F8-J
HYMD264M646B(L)F8-M
HYMD264M646B(L)F8-K
HYMD264M646B(L)F8-H
HYMD264M646B(L)F8-L
V
DD
=2.5V
V
DDQ
=2.5V
Power Supply
Clock Frequency
166MHz (*DDR333)
133MHz (*DDR266)
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
CL-tRCD-tRP
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2.5-3-3
Form Factor
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004
2
HYMD264M646B(L)F8-J/M/K/H/L
PIN DESCRIPTION
Pin
CK0, /CK0, CK1, /CK1
CS0, CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
PIN ASSIGNMENT
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Name
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
DQ16
DQ17
VDD
DQS2
DQ18
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Name
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Name
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
NC
NC
VSS
NC
NC
VDD
NC
DU
VSS
NC
NC
VDD
CKE1
NC
A12
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Name
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
NC
NC
VSS
NC
NC
VDD
NC
DU
VSS
VSS
VDD
VDD
CKE0
DU
A11
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Name
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
/WE
/CS0
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Name
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/CS1
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Name
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Name
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Rev. 0.2 / Apr. 2004
3
HYMD264M646B(L)F8-J/M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
/CS1
/CS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
/CS
DQS
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D0
I/O3
I/O4
I/O5
I/O6
I/O7
D8
D4
D12
D12
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D1
D9
D5
D13
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D2
D10
D6
D14
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D3
D11
D7
D15
VDD SPD
VDD /VDDQ
SPD
Serial PD
DO-D15
SCL
DO-D15
DO-D15
Strap:see Note 4
SDA
WP
A0
A1
A2
VREF
VSS
VDDID
SA0 SA1 SA2
BA0-BA1
A0-A12
CKE1
/RAS
/CAS
CKE0
/WE
BA0-BA1 : SDRAMs D0-D15
A0-A12 : SDRAMs D0-D15
CKE : SDRAMs D8-D15
/RAS : SDRAMs D0-D15
/CAS : SDRAMs D0-D15
CKE : SDRAMs D0-D7
/WE : SDRAMs D0-D15
Note :
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms ± 5%.
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD
≠
VDDQ
Rev. 0.2 / Apr. 2004
4
HYMD264M646B(L)F8-J/M/K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature (Ambient)
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
1.0 x # of Components
260 / 10
Rating
o
Unit
C
o
C
V
V
V
mA
W
o
C
/ Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA= 0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
Min
2.3
2.3
V
REF
+ 0.15
-0.3
V
REF
- 0.04
1.15
Typ.
2.5
2.5
-
-
V
REF
1.25
Max
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
1.35
Unit
V
V
V
V
V
V
3
2
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA= 0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+ 0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2 / Apr. 2004
5
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