74ALVC162836A
Rev. 3 — 6 April 2018
20-bit registered driver with inverted register enable and
30 Ω termination resistors; 3-state
Product data sheet
1
General description
The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output
enable (OE), latch enable (LE) and clock inputs (CP).
When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is
held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-
data is stored in the latch/flip-flop.
The 74ALVC162836A is designed with 30 Ω series resistors in both HIGH or LOW output
stages.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not affect the state of the
latch/flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied
to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 12 mA at 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
Integrated 30 Ω termination resistors
Diode clamps to V
CC
and GND on all inputs
Input diodes to accommodate strong drivers
Complies with JEDEC standards:
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
–
CDM JESD22-C101E exceeds 1000 V
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
74ALVC162836A
3
Ordering information
Package
Temperature range Name
Description
Version
−40 °C to +85 °C
TSSOP56
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Table 1. Ordering information
Type number
74ALVC162836ADGG
4
Functional diagram
1
OE
56
CP
29
LE
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
EN5
3C4
G7
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
OE
CP
LE
A1
D
LE
CP
aaa-026917
Y1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
4D
1, 2
8D
5, 6
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
aaa-028395
Figure 1. Logic diagram (one channel)
V
CC
Figure 2. IEC logic symbol
A1
002aac725
Figure 3. Typical input (data or control)
74ALVC162836A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 6 April 2018
2 / 15
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
74ALVC162836A
5
Pinning information
5.1 Pinning
74ALVC162836A
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
1
2
3
4
5
6
7
8
9
56 CP
55 A1
54 A2
53 GND
52 A3
51 A4
50 V
CC
49 A5
48 A6
47 A7
46 GND
45 A8
44 A9
43 A10
42 A11
41 A12
40 A13
39 GND
38 A14
37 A15
36 A16
35 V
CC
34 A17
33 A18
32 GND
31 A19
30 A20
29 LE
aaa-028396
Y7 10
GND 11
Y8 12
Y9 13
Y10 14
Y11 15
Y12 16
Y13 17
GND 18
Y14 19
Y15 20
Y16 21
V
CC
22
Y17 23
Y18 24
GND 25
Y19 26
Y20 27
n.c. 28
Figure 4. Pin configuration TSSOP56 (SOT364-1)
74ALVC162836A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 6 April 2018
3 / 15
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
74ALVC162836A
5.2 Pin description
Table 2. Pin description
Symbol
A1, A2, A3, A4, A5,
A6, A7, A8, A9, A10,
A11, A12, A13, A14, A15,
A16, A17, A18, A19, A20
Y1, Y2, Y3, Y4, Y5,
Y6, Y7, Y8, Y9, Y10,
Y11, Y12, Y13, Y14, Y15,
Y16, Y17, Y18, Y19, Y20
n.c.
LE
OE
CP
GND
V
CC
Pin
55, 54, 52, 51, 49,
48, 47, 45, 44, 43,
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2, 3, 5, 6, 8,
9, 10, 12, 13, 14,
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
28
29
1
56
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data inputs
data outputs
no connection
latch enable input (active LOW)
output enable input (active LOW)
clock input
(LOW-to-HIGH, edge-triggered)
ground (0 V)
supply voltage
6
Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock
transition.
Input
OE
H
L
L
L
L
L
L
LE
X
L
L
H
H
H
H
CP
X
X
X
↑
↑
H
L
An
X
L
H
L
H
X
X
Output
Yn
Z
L
H
L
H
Y
0
Y
0
[1]
[2]
[1] Y
0
= Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low.
[2] Y
0
= Output level before the indicated steady-state input conditions were established.
74ALVC162836A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 6 April 2018
4 / 15
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
74ALVC162836A
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
[2]
[1]
[1]
Conditions
Min
-0.5
-0.5
-0.5
-
-
-
-
-100
-65
-
Max
+4.6
+4.6
-50
±50
±50
100
-
+150
600
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
CC
+ 0.5 V
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 package: P
tot
derates linearly with 8 mW/K above 55 °C.
8
Recommended operating conditions
Parameter
supply voltage
Conditions
maximum speed performance
V
CC
= 2.5 V; C
L
= 30 pF
V
CC
= 3.3 V; C
L
= 50 pF
LOW-voltage applications
2.3
3.0
1.2
0
0
operating in free-air
V
CC
= 2.3 V to 3.0 V
V
CC
= 3.0 V to 3.6 V
-40
0
0
-
-
-
-
-
-
-
-
2.7
3.6
3.6
V
CC
V
CC
+85
20
10
V
V
V
V
V
°C
ns/V
ns/V
Min
Typ
Max
Unit
Table 5. Recommended operating conditions
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
input voltage
output voltage
ambient temperature
input transition rise and fall rate
74ALVC162836A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 6 April 2018
5 / 15
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