Rev. 2.2
_10
CMOS SERIAL E
2
PROM
S-93C46A/56A/66A
The S-93C46A/56A/66A is high speed, low power 1K/2K/4K-bit E
2
PROM with
a wide operating voltage range. It is organized as 64-word
×16-bit,
128-
word×16-bit, 256-word×16-bit, respectivly. Each is capable of sequential
read, at which time addresses are automatically incremented in 16-bit blocks.
The instruction code is compatible with the NM93CS46/56/66.
Features
Low power consumption
Standby : 1.0
µ
A Max. (V
CC
=5.5 V)
Operating : 0.8 mA Max. (V
CC
=5.5 V)
: 0.4 mA Max. (V
CC
=2.5 V)
Wide operating voltage range
Read/Write : 1.8 to 5.5 V
Sequential read capable
Endurance : 10 cycles/word
Data retention : 10 years
S-93C46A : 1K bits NM93CS46 instruction code compatible
S-93C56A : 2K bits NM93CS56 instruction code compatible
S-93C66A : 4K bits NM93CS66 instruction code compatible
6
Pin Assignment
8-pin DIP (PKG drawing code : DP008-A,DP008-C,DP008-E)
8-pin SOP (PKG drawing code : FJ008-D,FJ008-E)
8-pin MSOP (PKG drawing code : FN008-A)
8-pin TSSOP (PKG drawing code : FT008-B)
Pin Assignment
8-pin DIP
Top view
CS
SK
DI
DO
8-pin SOP1
Top view
8
7
6
5
VCC
NC
TEST
GND
NC
VCC
8-pin SOP2
Top view
TEST
GND
DO
DI
CS
SK
DI
DO
8-pin TSSOP
Top view
VCC
NC
TEST
GND
CS
SK
DI
DO
1
2
3
4
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
1
2
3
4
S-93C46AFT
S-93C56AFT
S-93C66AFT
8
7
6
5
VCC
NC
TEST
GND
S-93C46AFJ
S-93C56AFJ
S-93C66AFJ
S-93C46ADFJ
S-93C56ADFJ
S-93C66ADFJ
VCC
NC
TEST
GND
S-93C46ADP-1A
S-93C56ADP-1A
S-93C66ADP-1A
8-pin MSOP
Top view
1
2
3
4
8
7
6
5
CS
SK
DI
DO
* See
Dimensions
Pin Functions
Figure 1
Table 1
Pin Number
S-93C46AMFN
S-93C56AMFN
S-93C66AMFN
Name
DIP
CS
SK
DI
DO
GND
TEST
NC
V
CC
1
2
3
4
5
6
7
8
SOP1
3
4
5
6
7
8
1
2
SOP2
1
2
3
4
5
6
7
8
TSSOP MSOP
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
Function
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
Test pin (normally kept open)
(can be connected to GND or Vcc)
No Connection
Power supply
Seiko Instruments Inc.
1
CMOS SERIAL E
2
PROM
S-93C46A/56A/66A
Rev. 2.2
_10
Block Diagram
Memory array
Address
decoder
V
CC
GND
Data register
DI
Mode decode logic
CS
Output buffer
DO
SK
Clock generator
Figure 2
Instruction Set
Table 2
Instruction
Start
Bit
Op
Code
S-93C46A
READ
WRITE
(Read data)
(Write data)
1
1
1
1
1
1
1
10
01
11
00
00
00
00
A
5
to A
0
A
5
to A
0
A
5
to A
0
01xxxx
10xxxx
11xxxx
00xxxx
S-93C56A
XA
6
to A
0
XA
6
to A
0
XA
6
to A
0
01xxxxxx
10xxxxxx
11xxxxxx
00xxxxxx
S-93C66A
A
7
to A
0
A
7
to A
0
A
7
to A
0
01xxxxxx
10xxxxxx
11xxxxxx
00xxxxxx
D
15
to D
0
Output*1
D
15
to D
0
Input
Address
Data
ERASE (Erase data)
WRAL
ERAL
EWEN
EWDS
x :
*1 :
*2 :
(Write all)*2
(Erase all)*2
(Program enable)
(Program disable)
D
15
to D
0
Input
Doesn’t matter.
Addresses are continuously incremented.
Valid only at Vcc = 2.5 V to 5.5 V.
Absolute Maximum Ratings
Table 3
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature under bias
Storage temperature
Symbol
V
CC
V
IN
V
OUT
T
bias
T
stg
Ratings
-0.3 to +7.0
-0.3 to V
CC
+0.3
-0.3 to V
CC
-50 to +95
-65 to +150
Unit
V
V
V
°C
°C
2
Seiko Instruments Inc.
FPGA/CPLD
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