512MB, 1GB (x64)
200-PIN DDR SODIMM
SMALL-OUTLINE
DDR SDRAM DIMM
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates: PC1600, PC2100, and PC2700
• Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR
SDRAM components
• 512MB (64 Meg x 64), 1GB (128 Meg x 64)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
MT16VDDF6464H – 512MB
MT16VDDF12864H – 1GB
For the latest data sheet, please refer to the Micron
â
Web
site:
www.micron.com/moduleds
Figure 1: 200-Pin SODIMM (MO-224)
512MB Module
1GB Module
OPTIONS
MARKING
G
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
1
• Frequency/CAS Latency
2
167 MHz (333 MT/s) CL = 2.5
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2.5
100 MHz (200 MT/s) CL = 2
NOTE:
Y
-335
-262
-26A
-265
-202
1. Contact factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) latency.
Table 1:
Address Table
512MB
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 8
2K (A0–A9, A11)
2 (S0#, S1#)
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
2 (S0#, S1#)
Refresh Count
Device Row Addressing
Device Bank Addressing
Device Configuration
Device Column Addressing
Module Rank Addressing
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 8/03 EN
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
CONFIGURATION
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
TRANSFER
RATE
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
MEMORY CLOCK/
DATA BIT RATE
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
PART NUMBER
MT16VDDF6464HG-335__
MT16VDDF6464HY-335__
MT16VDDF6464HG-262__
MT16VDDF6464HY-262__
MT16VDDF6464HG-26A__
MT16VDDF6464HY-26A__
MT16VDDF6464HG-265__
MT16VDDF6464HY-265__
MT16VDDF6464HG-202__
MT16VDDF6464HY-202__
MT16VDDF12864HG-335__
MT16VDDF12864HY-335__
MT16VDDF12864HG-262__
MT16VDDF12864HY-262__
MT16VDDF12864HG-26A__
MT16VDDF12864HY-26A__
MT16VDDF12864HG-265__
MT16VDDF12864HY-265__
MT16VDDF12864HG-202__
MT16VDDF12864HY-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current Revision codes. Example: MT16VDDF6464HG-265A1.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 8/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
DNU
DNU
V
SS
DNU
DNU
V
DD
DNU
NC
V
SS
DNU
DNU
V
DD
CKE1
NC
A12
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A9
V
SS
A7
A5
A3
A1
V
DD
A10
BA0
WE#
S0#
NC
V
SS
DQ32
DQ33
V
DD
DQS4
DQ34
V
SS
DQ35
DQ40
V
DD
DQ41
DQS5
V
SS
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ42
DQ43
V
DD
V
DD
V
SS
V
SS
DQ48
DQ49
V
DD
DQS6
DQ50
V
SS
DQ51
DQ56
V
DD
DQ57
DQS7
V
SS
DQ58
DQ59
V
DD
SDA
SCL
V
DDSPD
NC
Table 4:
Pin Assignment
(200-Pin SODIMM Back)
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
DNU
DNU
V
SS
DNU
DNU
V
DD
DNU
DNU
V
SS
V
SS
V
DD
V
DD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS#
CAS#
S1#
NC
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
DD
CK1#
CK1
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
V
SS
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0#
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
DD
DM2
DQ22
Figure 2: Module Layout
Front View
U1
U2
U3
U4
U5
U6
Front View
U17
U1
U2
U3
U4
U7
U17
U8
U5
U6
U7
U8
PIN 1
(all odd pins)
PIN 199
PIN 1
(all odd pins)
PIN 199
Back View
U9
U10
U11
U12
U13
U14
Back View
U9
U10
U11
U12
U15
U16
U13
U14
U15
U16
PIN 200
(all even pins)
PIN 2
PIN 200
(all even pins)
PIN 2
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 8/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions
SYMBOL
WE#,
CAS#,RAS#
CK0, CK0#
CK1, CK1#
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK, and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after VDD is applied and
until CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
SSTL_2 reference voltage.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
118, 119, 120
35, 37, 158, 160
95, 96
CKE0, CKE1
Input
121, 122
S0#, S1#
Input
116, 117
BA0, BA1
Input
99, 100, 101, 102, 105,106,
107, 108, 109, 110, 111, 112,
115
A0-A12
Input
1, 2
195
194, 196, 198
193
V
REF
SCL
SA0-SA2
SDA
Input
Input
Input
Input/
Output
Input
12, 26, 48, 62, 134, 148, 170,
184
DM0-DM7
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 8/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions (Continued)
SYMBOL
DQS0-DQS7
TYPE
Input/
Output
Input/
Output
DESCRIPTION
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
11, 25, 47, 61, 133, 147, 169,
183
5, 6, 7, 8, 13, 14, 17, 18, 19,
20, 23, 24, 29, 30, 31, 32, 41,
42, 43, 44, 49, 50, 53, 54, 55,
56, 59, 60, 65, 66, 67, 68, 127,
128, 129, 130, 135, 136, 139,
140, 141, 142, 145, 146, 151,
152, 153, 154, 163, 164, 165,
166, 171, 172, 175, 176, 177,
178, 181, 182, 187, 188, 189,
190
9, 10, 21, 22, 33, 34, 36, 45,
46, 57, 58, 69, 70, 81, 82, 92,
93, 94, 113, 114, 131, 132,
143, 144, 155, 156, 157, 167,
168, 179, 180, 191, 192
3, 4, 15, 16, 27, 28, 38, 39, 40,
51, 52, 63, 64, 75, 76, 87, 88,
90, 103, 104, 125, 126, 137,
138, 149, 150, 159, 161, 162,
173, 174, 185, 186, 200
197
85, 97, 98, 123, 124, 199
71, 72, 73, 74, 77, 78, 79, 80,
83, 84, 86, 89, 91
DQ0-DQ63
V
DD
Supply
Power Supply: +2.5V ±0.2V.
V
SS
Supply
Ground.
V
DDSPD
NC
DNU
Supply
—
—
Serial EEPROM positive power supply: +2.3V to +3.6V
No Connect: These pins should be left unconnected.
Do Not Use: These pins are not connected on this module, but
are assigned pins on other modules in this product family.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 8/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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