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HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
2Gb NAND FLASH
HY27UF(08/16)2G2B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.2 / Jan. 2008
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HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
Document Title
2Gbit (256Mx8bit) NAND Flash Memory
Revision History
Revision No.
0.0
Initial Draft.
1) Add ULGA Package.
0.1
- Figures & texts are added.
2) Change tRCBSY to tRBSY
3) Change figure 13
0.2
1) Delete Preliminary
Jan. 09. 2008
Sep. 11. 2007
Preliminary
History
Draft Date
Jul. 03. 2007
Remark
Preliminary
Rev 0.2 / Jan. 2008
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HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
MULTIPLANE ARCHITECTURE
- Array is split into two independent planes. Parallel
Operations on both planes are available, halving
Program and erase time.
NAND INTERFACE
- x8/x16 bus width.
- Address/ Data Multiplexing
- Pinout compatiblity for all densities
SUPPLY VOLTAGE
- 3.3V device : Vcc = 2.7 V ~3.6 V
MEMORY CELL ARRAY
- x8 : (2K + 64) bytes x 64 pages x 2048 blocks
- x16 : (1K + 32) words x 64 pages x 2048 blocks
PAGE SIZE
- (2K + 64 spare) Bytes
- (1K + 32 spare) Words
BLOCK SIZE
- (128K + 4Kspare) Bytes
- (64K + 2Kspare) Words
PAGE READ / PROGRAM
- Random access : 25us (max.)
- Sequential access : 25ns (min.)
- Page program time : 200us (typ.)
- Multi-page program time (2 pages) : 200us (typ.)
COPY BACK PROGRAM
- Automatic block download without latency time
FAST BLOCK ERASE
- Block erase time: 1.5ms (typ.)
- Multi-block erase time (2 blocks) : 1.5ms (typ.)
CACHE READ
- Internal (2048 + 64) Byte buffer to improve the read
throughtput.
Rev 0.2 / Jan. 2008
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STATUS REGISTER
- Normal Status Register (Read/Program/Erase)
- Extended Status Register (EDC)
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle : Device Code
- 3rd cycle : Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle : Page size, Block size, Organization, Spare
size
- 5th cycle : Multiplane information
CHIP ENABLE DON’T CARE
- Simple interface with microcontroller
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions.
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UF(08/16)2G2B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UF(08/16)2G2B-T (Lead)
- HY27UF(08/16)2G2B-TP (Lead Free)
- HY27UF082G2B-F(P)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27UF082G2B-F (Lead)
- HY27UF082G2B-FP (Lead Free)
- HY27UF082G2B-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UF082G2B-UP (Lead Free)
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HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
1.SUMMARY DESCRIPTION
Hynix NAND HY27UF(08/16)2G2B Series have 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid state
mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typi-
cal 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block.
Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data
input/output as well as command input.
This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of
footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The
on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where
required, and internal verification and margining of data. The modify operations can be locked using the WP input. The
output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple mem-
ories the R/B pins can be connected all together to provide a global status signal.
The copy back function allows the optimization of defective blocks management. When a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error
every 528byte (x8) or 1bit error out of every 264-word (x16) can be detected. Due to this feature, it is no more nor neces-
sary nor recommended to use external 2-bit ECC to detect copy back operation errors. Data read out after copy back read
(both for single and multiplane cases) is allowed.
Even the write-intensive systems can take advantage of the HY27UF(08/16)2G2B Series extended reliability of 100K pro-
gram/erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE
don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a micro-
controller, since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27UF(08/16)2G2B Series are available in 48-TSOP1 12 x 20 mm, 63-FBGA 9 x 11mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27UF082G2B
HY27UF162G2B
ORGANIZATION
x8
x16
Vcc RANGE
2.7V ~ 3.6V
PACKAGE
48-TSOP1, 63-FBGA, 52-ULGA
48-TSOP1
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HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Input / Outputs (x16 only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.2 / Jan. 2008
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FPGA/CPLD
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