LTC4257-1
IEEE 802.3af PD
Power over Ethernet Interface
Controller with Dual Current Limit
FEATURES
s
s
s
s
s
s
s
s
s
DESCRIPTIO
Complete Power Interface Port for IEEE 802
®
.3af
Powered Devices (PDs)
Onboard 100V, 400mA Power MOSFET
Precision Dual Level Current Limit
Onboard 25k Signature Resistor with Disable
Programmable Classification Current (Class 0-4)
Undervoltage Lockout
Thermal Overload Protection
Power Good Signal
Available in 8-Pin SO and Low Profile (3mm
×
3mm)
DFN Packages
APPLICATIO S
s
s
s
IP Phone Power Management
Wireless Access Points
Telecom Power Control
The LTC
®
4257-1 provides complete signature and power
interface functions for a device operating in an IEEE
802.3af Power over Ethernet (PoE) system. The LTC4257-1
simplifies Powered Device (PD) design by incorporating
the 25k signature resistor, classification current source,
input current limit, undervoltage lockout, thermal over-
load protection, signature disable and power good signal-
ling, all in a single 8-pin package. The LTC4257-1 includes
a precision, dual level current limit circuit. This allows it to
charge large load capacitors and interface with legacy
Power over Ethernet systems while maintaining compat-
ibility with the current IEEE 802.3af specification. By
incorporating a high voltage power MOSFET onboard, the
LTC4257-1 provides the system designer with reduced
cost while also saving board space.
The LTC4257-1 can interface directly with a variety of Lin-
ear Technology DC/DC converter products to provide a cost
effective power solution for IP phones, wireless access
points and other PDs. Linear Technology also provides
network power controllers for Power Sourcing Equipment
(PSE) applications.
The LTC4257-1 is available in the 8-pin SO and low profile
(3mm
×
3mm) DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
802 is a registered trademark of Institute of Electrical and Electronics Engineers, Inc.
TYPICAL APPLICATIO
Powered Device (PD)
~
–48V FROM
POWER SOURCING
EQUIPMENT
(PSE)
+
0.1µF
SMAJ58A
LTC4257-1
GND
R
CLASS
SIGDISA
5µF
MIN
100k
+
DF01SA
SWITCHING
POWER SUPPLY
SHDN
RTN
~
–
R
CLASS
V
IN
PWRGD
V
OUT
U
V
IN
U
U
+
3.3V
TO LOGIC
42571 TA01
–
42571fa
1
LTC4257-1
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
Operating Ambient Temperature Range
LTC4257C-1 ............................................ 0°C to 70°C
LTC4257I-1 ......................................... –40°C to 85°C
Storage Temperature Range
S8 Package ....................................... – 65°C to 150°C
DD Package ...................................... – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
V
IN
Voltage ............................................. 0.3V to – 100V
V
OUT
, SIGDISA,
PWRGD Voltage ...................... V
IN
+ 100V to V
IN
– 0.3V
R
CLASS
Voltage ............................ V
IN
+ 7V to V
IN
– 0.3V
PWRGD Current .................................................. 10mA
R
CLASS
Current .................................................. 100mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW
NC 1
R
CLASS
2
NC 3
V
IN
4
8
7
6
5
GND
SIGDISA
PWRGD
V
OUT
ORDER PART
NUMBER
LTC4257CS8-1
LTC4257IS8-1
S8 PART MARKING
42571
4257I1
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 150°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL
V
IN
PARAMETER
Supply Voltage
Maximum Operating Voltage
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
IC Supply Current when ON
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
CONDITIONS
Voltage with Respect to GND Pin (Notes 4, 5, 6)
q
q
q
q
q
I
IN_ON
I
IN_CLASS
∆I
CLASS
R
SIGNATURE
R
INVALID
V
IN
= – 48V, Pins 5, 6, 7 Floating
IC Supply Current During Classification V
IN
= – 17.5V, Pins 2, 7 Floating, V
OUT
Tied to GND
(Note 7)
Current Accuracy During Classification 10mA < I
CLASS
< 40mA, – 12.5V
≤
V
IN
≤
– 21V,
(Notes 8, 9)
Signature Resistance
Invalid Signature Resistance
–1.5V
≤
V
IN
≤
–9.5V, V
OUT
Tied to GND,
IEEE 802.3af 2-Point Measurement (Notes 4, 5)
– 1.5V
≤
V
IN
≤
– 9.5V, SIGDISA and V
OUT
Tied to GND, IEEE 802.3af 2-Point Measurement
(Notes 4, 5)
With Respect to V
IN
,
High Level Invalidates Signature (Note 10)
With Respect to V
IN
,
Low Level Enables Signature
V
IH
V
IL
Signature Disable
High Level Input Voltage
Signature Disable
Low Level Input Voltage
2
U
U
W
W W
U
W
TOP VIEW
NC
R
CLASS
NC
V
IN
1
2
3
4
8
7
6
5
GND
SIGDISA
PWRGD
V
OUT
ORDER PART
NUMBER
LTC4257CDD-1
LTC4257IDD-1
DD PART MARKING
DD PACKAGE
8-LEAD (3mm
×
3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD TO BE SOLDERED TO
ELECTRICALLY ISOLATED PCB HEATSINK
LBFZ
MIN
TYP
MAX
– 57
– 9.5
– 21
– 37.2
– 31.5
3
0.65
±3.5
UNITS
V
V
V
V
V
mA
mA
%
kΩ
kΩ
– 1.5
– 12.5
– 34.8
– 29.3
0.35
–36.0
–30.5
0.50
q
q
q
q
q
23.25
9
26.00
11.8
q
q
3
57
0.45
V
V
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LTC4257-1
ELECTRICAL CHARACTERISTICS
SYMBOL
R
INPUT
V
PG_OUT
V
PG_THRES_FALL
V
PG_THRES_RISE
I
PG_LEAK
R
ON
I
OUT_LEAK
I
LIMIT_HIGH
Power Good Leakage
On-Resistance
V
OUT
Leakage
Input Current Limit, High Level
PARAMETER
Signature Disable
Input Resistance
Power Good Output Low Voltage
Power Good Trip Point
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
CONDITIONS
With Respect to V
IN
q
MIN
100
TYP
MAX
UNITS
kΩ
I = 1mA, V
IN
= – 48V, PWRGD Referenced to V
IN
V
IN
= –48V, Voltage Between V
IN
and V
OUT
V
OUT
Falling
V
OUT
Rising
V
IN
= 0V, PWRGD FET Off, V
PWRGD
= 57V
I = 350mA, V
IN
= – 48V, Measured from V
IN
to V
OUT
(Note 9)
V
IN
= 0V, Power MOSFET Off, V
OUT
= 57V (Note 11)
V
IN
= – 48V, V
OUT
= –43V (Notes 12, 13)
0°C
≤
T
A
≤
70°C
–40°C
≤
T
A
≤
85°C
V
IN
= – 48V, V
OUT
= –43V (Notes 12, 13)
(Notes 12, 14)
q
q
q
q
0.5
1.3
2.7
1.5
3.0
1.0
1.7
3.3
1
1.6
2.0
150
350
340
100
375
375
140
140
400
400
180
V
V
V
µA
Ω
Ω
µA
mA
mA
mA
°C
q
q
q
q
q
I
LIMIT_LOW
T
SHUTDOWN
Input Current Limit, Low Level
Thermal Shutdown Trip Temperature
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltages are with respect to GND pin unless otherwise noted.
Note 3:
The LTC4257-1 operates with a negative supply voltage in the
range of –1.5V to –57V. To avoid confusion, voltages in this data sheet are
always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and a
“rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4:
The LTC4257-1 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specified in the
Electrical Characteristics are with respect to LTC4257-1 pins and are
designed to meet IEEE 802.3af specifications when these diode drops are
included. See Applications Information.
Note 5:
Signature resistance is measured via the 2-point
∆V/∆I
method as
defined by IEEE 802.3af. The LTC4257-1 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75kΩ and 26.25kΩ and meet IEEE
802.3af specifications. The minimum probe voltages measured at the
LTC4257-1 pins are –1.5V and –2.5V. The maximum probe voltages are
–8.5V and –9.5V.
Note 6:
The LTC4257-1 includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the
LTC4257-1 will power up from a voltage source with 20Ω series
resistance on the first trial.
Note 7:
I
IN_CLASS
does not include classification current programmed at
Pin 2. Total supply current in classification mode will be I
IN_CLASS
+ I
CLASS
(see Note 8).
Note 8:
I
CLASS
is the measured current flowing through R
CLASS
.
∆I
CLASS
accuracy is with respect to the ideal current defined as
I
CLASS
= 1.237/R
CLASS
. The current accuracy specification does not
include variations in R
CLASS
resistance. The total classification current for
a PD also includes the IC quiescent current (I
IN_CLASS
). See Applications
Information.
Note 9:
For the DD package, this parameter is assured by design and
wafer level testing.
Note 10:
To disable the 25k signature, tie SIGDISA to GND (±0.1V) or hold
SIGDISA high with respect to V
IN
. See Applications Information.
Note 11:
I
OUT_LEAK
includes current drawn at the V
OUT
pin by the power
good status circuit. This current is compensated for in the 25kΩ signature
resistance and does not affect PD operation.
Note 12:
The LTC4257-1 includes thermal protection. In the event of an
overtemperature condition, the LTC4257-1 will turn off the power MOSFET
until the part cools below the overtemperature limit. The LTC4257-1 is
also protected against thermal damage from incorrect classification
probing by the PSE. If the LTC4257-1 exceeds the overtemperature trip
point, the classification load current is disabled.
Note 13:
The LTC4257-1 includes dual level input current limit. At turn-on,
before C1 is charged, the LTC4257-1 current level is set to the low level.
After C1 is charged and the V
OUT
– V
IN
voltage difference is below the
power good threshold, the LTC4257-1 switches to high level current limit.
The LTC4257-1 stays in high level current limit until the input voltage
drops below the UVLO turn-off threshold.
Note 14:
This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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3
LTC4257-1
TYPICAL PERFOR A CE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
0.5
T
A
= 25°C
50
0.4
INPUT CURRENT (mA)
INPUT CURRENT (mA)
INPUT CURRENT (mA)
0.3
0.2
0.1
0
0
–2
–4
–6
INPUT VOLTAGE (V)
Input Current vs Input Voltage
3
EXCLUDES ANY LOAD CURRENT
T
A
= 25°C
SIGNATURE RESISTANCE (kΩ)
NORMALIZED UVLO THRESHOLD (%)
INPUT CURRENT (mA)
2
1
0
–40
–50
–45
–55
INPUT VOLTAGE (V)
Power Good Output Low Voltage
vs Current
4
120
T
A
= 25°C
CURRENT LIMIT (mA)
V
OUT
CURRENT (µA)
3
V
PG_OUT
(V)
2
1
0
0
2
6
4
CURRENT (mA)
4
U W
–8
4357 G01
Input Current vs Input Voltage
T
A
= 25°C
CLASS 4
40
Input Current vs Input Voltage
12.0
11.5
11.0
10.5
10.0
9.5
85°C
–40°C
CLASS 1 OPERATION
30
CLASS 3
20
CLASS 2
CLASS 1
10
CLASS 0
–10
0
0
–10
–20
–30
–40
INPUT VOLTAGE (V)
–50
–60
9.0
–12
–14
–20
–18
–16
INPUT VOLTAGE (V)
–22
42571 G03
42571 G02
Signature Resistance
vs Input Voltage
28
RESISTANCE =
∆V
= V2 – V1
∆I
I
2
– I
1
27 DIODES: S1B
T
A
= 25°C
IEEE UPPER LIMIT
Normalized UVLO Threshold
vs Temperature
2
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
1
26
25
24
LTC4257-1 ONLY
23
22
V1: –1
V2: –2
IEEE LOWER LIMIT
LTC4257-1 + 2 DIODES
0
–1
–60
42571 G04
–3
–4
–7
–5
–8
–6
INPUT VOLTAGE (V)
–9
–10
42571 G05
–2
–40
–20
60
0
20
40
TEMPERATURE (°C)
80
42571 G06
V
OUT
Leakage Current
V
IN
= 0V
T
A
= 25°C
Current Limit vs Input Voltage
400
85°C
–40°C
HIGH CURRENT MODE
90
300
60
200
85°C
–40°C
30
LOW CURRENT MODE
0
8
10
42571 G07
0
40
V
OUT
PIN VOLTAGE (V)
20
60
42571 G08
100
–40
–50
–45
–55
INPUT VOLTAGE (V)
–60
42571 G09
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LTC4257-1
PI FU CTIO S
NC (Pin 1):
No Internal Connection.
R
CLASS
(Pin 2):
Class Select Input. Used to set the current
value the LTC4257-1 maintains during classification. Con-
nect a resistor between R
CLASS
and V
IN
(see Table 2).
NC (Pin 3):
No Internal Connection.
V
IN
(Pin 4):
Power Input. Tie to system – 48V through the
input diode bridge.
V
OUT
(Pin 5):
Power Output. Supplies – 48V to the PD load
through an internal power MOSFET that limits input cur-
rent. V
OUT
is high impedance until the input voltage rises
above the turn-on UVLO threshold. The output is then
current limited. See Applications Information.
PWRGD (Pin 6):
Power Good Output, Open-Drain. Signals
to the PD load that the LTC4257-1 MOSFET is on and that
the PD’s DC/DC converter can start operation. Low imped-
ance indicates power is good. PWRGD is high impedance
during detection, classification and in the event of a
thermal overload. PWRGD is referenced to V
IN
.
SIGDISA (Pin 7):
Signature Disable Input. Allows the PD
to command the LTC4257-1 to present an invalid signa-
ture resistance and to remain inactive. Connecting SIGDISA
to GND lowers the signature resistance to an invalid value.
If left floating, SIGDISA is internally pulled to V
IN
. If
unused, tie SIGDISA to V
IN
.
GND (Pin 8):
Ground. Tied to system ground and power
return through the input diode bridge.
BLOCK DIAGRA
NC 1
R
CLASS
2
NC 3
V
IN
4
BOLD LINE INDICATES HIGH CURRENT PATH
W
U
U
U
CLASSIFICATION
CURRENT LOAD
1.237V
+
–
9k
EN
25k SIGNATURE
RESISTOR
16k
SIGNATURE DISABLE
8
GND
7
SIGDISA
POWER GOOD
CONTROL
CIRCUITS
6
PWRGD
375mA
140mA
+
–
EN
INPUT
CURRENT
LIMIT
0.3Ω
5 V
OUT
42571 BD
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