HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
◆
70V7339S
Features:
◆
◆
◆
◆
◆
◆
512K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
–
64 independent 8K x 18 banks
– 9 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
◆
◆
◆
◆
◆
◆
◆
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/FT
L
OPT
L
CLK
L
ADS
L
CNTEN
L
REPEAT
L
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
PL/FT
R
OPT
R
CLK
R
ADS
R
CNTEN
R
REPEAT
R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
MUX
8Kx18
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
I/O
0L-17L
I/O
CONTROL
MUX
8Kx18
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
0R-17R
A
12L
A
0L
BA
5L
BA
4L
BA
3L
BA
2L
BA
1L
BA
0L
ADDRESS
DECODE
ADDRESS
DECODE
A
12R
A
0R
BA
5R
BA
4R
BA
3R
BA
2R
BA
1R
BA
0R
BANK
DECODE
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 18
for details.
MUX
,
TDI
TDO
JTAG
TMS
TCK
TRST
5628 drw 01
OCTOBER 2019
1
DSC 5628/12
©2019 Integrated Device Technology, Inc.
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
8Kx18 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 8Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
register, the IDT70V7339 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE
0
and CE
1
, permits the on-chip circuitry of each
port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.
The 70V7339 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(V
DD
) remains at 3.3V. Please refer also to the
functional description on page 18.
Pin Configuration
(1,2,3,4)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
IO
9L
B1
NC
B2
V
SS
B3
TDO
B4
NC
B5
BA
3L
B6
A
12L
B7
A
8L
B8
NC
B9
V
DD
B10
CLK
L
CNTEN
L
A
4L
B11
B12
B13
A
0L
B14
OPT
L
B15
NC
B16
V
SS
B17
NC
C1
V
SS
C2
NC
C3
TDI
C4
BA
4L
C5
BA
0L
C6
A
9L
C7
NC
C8
CE
0L
C9
V
SS
C10
ADS
L
C11
A
5L
C12
A
1L
C13
V
SS
C14
V
DDQR
I/O
8L
C15
C16
NC
C17
V
DDQL
I/O
9R
V
DDQR
PL/FT
L
BA
5L
BA
1L
D1
D2
D3
D4
D5
D6
A
10L
D7
UB
L
D8
CE
1L
D9
V
SS
D10
R/W
L
D11
A
6L
D12
A
2L
D13
V
DD
D14
I/O
8R
D15
NC
D16
V
SS
D17
NC
E1
V
SS
E2
I/O
10L
E3
NC
E4
BA
2L
A
11L
A
7L
LB
L
V
DD
OE
L
REPEAT
L
A
3L
V
DD
NC
E14
V
DDQL
I/O
7L
E15
E16
I/O
7R
E17
I/O
11L
F1
NC
F2
V
DDQR
I/O
10R
F3
F4
I/O
6L
F14
NC
F15
V
SS
F16
NC
F17
V
DDQL
I/O
11R
G1
G2
NC
G3
V
SS
G4
V
SS
G14
I/O
6R
G15
NC
G16
V
DDQR
G17
NC
H1
V
SS
H2
I/O
12L
H3
NC
H4
NC
V
DDQL
I/O
5L
H15
H16
NC
H17
V
DD
J1
NC
J2
V
DDQR
I/O
12R
J3
J4
70V7339
BF208
(5)
BFG208
(5)
208-Pin fpBGA
Top View
(6)
H14
V
DD
J14
NC
J15
V
SS
J16
I/O
5R
J17
V
DDQL
K1
V
DD
K2
V
SS
K3
V
SS
K4
V
SS
K14
V
DD
K15
V
SS
V
DDQR
K16
K17
I/O
14R
L1
V
SS
L2
I/O
13R
L3
V
SS
L4
I/O
3R
L14
V
DDQL
I/O
4R
L15
L16
V
SS
L17
NC
M1
I/O
14L
V
DDQR
I/O
13L
M2
M3
M4
NC
M14
I/O
3L
M15
V
SS
M16
I/O
4L
M17
V
DDQL
N1
NC
N2
I/O
15R
N3
V
SS
N4
V
SS
N14
NC
N15
I/O
2R
V
DDQR
N16
N17
NC
P1
V
SS
P2
NC
P3
I/O
15L
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
I/O
1R
V
DDQL
P14
P15
NC
P16
I/O
2L
P17
I/O
16R
I/O
16L
V
DDQR
R1
R2
R3
NC
R4
TRST
BA
3R
R5
R6
A
12R
R7
A
8R
R8
NC
R9
V
DD
R10
CLK
R
CNTEN
R
A
4R
R11
R12
R13
NC
R14
I/O
1L
R15
V
SS
R16
NC
R17
V
SS
T1
NC
T2
I/O
17R
TCK
T3
T4
BA
4R
BA
0R
T5
T6
A
9R
T7
NC
T8
CE
0R
T9
V
SS
T10
ADS
R
T11
A
5R
T12
A
1R
T13
V
SS
T14
V
DDQL
I/O
0R
V
DDQR
T15
T16
T17
NC
U1
I/O
17L
V
DDQL
TMS
U2
U3
U4
BA
5R
BA
1R
U5
U6
A
10R
U7
UB
R
U8
CE
1R
U9
V
SS
U10
R/W
R
U11
A
6R
U12
A
2R
U13
V
SS
U14
NC
U15
V
SS
U16
NC
U17
V
SS
NC
PL/FT
R
NC
BA
2R
A
11R
A
7R
LB
R
V
DD
OE
R
REPEAT
R
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0L
5628 drw 02c
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
70V7339
BC256
(5)
BCG256
(5)
256-Pin BGA
Top View
(6)
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
B1
TDI
B2
NC
B3
BA
4L
BA1
L
A
11L
B4
B5
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
CNTEN
L
A
5L
B10
B11
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
TDO
C3
BA
5L
C4
BA
2L
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
REPEAT
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
NC
C15
NC
C16
NC
D1
I/O
9L
D2
V
SS
D3
BA
3L
D4
BA
0L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
CLK
L
ADS
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
PL/
FT
L
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
I/O
7R
F15
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
V
DD
G3
G4
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
6R
G12
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
H3
V
DDQR
V
SS
H4
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
5L
H13
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC
J3
V
DDQR
V
SS
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
V
DDQR
I/O
4R
I/O
3R
I/O
4L
K12
K13
K14
K15
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
V
SS
L3
L4
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
NC
L13
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
V
DD
M3
M4
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC
N3
V
DDQR
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
I/O
1L
N13
N14
N15
NC
N16
NC
P1
I/O
17R
P2
NC
P3
PL/
FT
R
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P4
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
NC
R1
I/O
17L
TMS
R2
R3
BA
3R
BA
0R
R4
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
R9
CLK
R
ADS
R
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
NC
T1
NC
T2
TRST
BA
5R
BA
2R
T3
T4
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
R/W
R
REPEAT
R
A
4R
T9
T10
T11
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
NC
TCK
NC
BA
4R
BA
1R
A
11R
A
8R
NC
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
5628 drw 02d
6.42
3
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
BA
0L
- BA
5L
A
0L
- A
12L
I/O
0L
- I/O
17L
CLK
L
PL/FT
L
ADS
L
CNTEN
L
REPEAT
L
LB
L
,
UB
L
V
DDQL
OPT
L
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
BA
0R
- BA
5R
A
0R
- A
12R
I/O
0R
- I/O
17R
CLK
R
PL/FT
R
ADS
R
CNTEN
R
REPEAT
R
LB
R
,
UB
R
V
DDQR
OPT
R
Chip Enables
Read/Write Enable
Output Enable
Bank Address
(4)
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat
(3)
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)
(1)
Option for selecting V
DDQX
(1,2)
Power (3.3V)
(1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5628 tbl 01
Names
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA
0L
- BA
5L
≠
BA
0R
- BA
5R
). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
6.42
4
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
3
X
X
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
L
L
L
L
X
CE
1
X
L
H
H
H
H
H
H
H
X
UB
X
X
H
H
L
L
H
L
L
X
LB
X
X
H
L
H
L
L
H
L
X
R/W
X
X
X
L
L
L
H
H
H
X
Upper Byte
I/O
9-17
High-Z
High-Z
High-Z
High-Z
D
IN
D
IN
High-Z
D
OUT
D
OUT
High-Z
Lower Byte
I/O
0-8
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
OUT
High-Z
D
OUT
High-Z
MODE
Deselected–Power Down
Deselected–Power Down
All Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to both Bytes
Read Lower Byte Only
Read Upper Byte Only
Read both Bytes
Outputs Disabled
5628 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, REPEAT
are set as appropriate for address access. Refer to Truth Table II for details.
3.
OE
is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address and Address Counter Control
(1,2,7)
Address
An
X
X
X
Previous
Address
X
An
An + 1
X
Addr
Used
An
An + 1
An + 1
An
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
REPEAT
(6)
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Set to last valid
ADS
load
5628 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W,
CE
0
, CE
1
,
UB/LB
and
OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
REPEAT
are independent of all other memory control signals including
CE
0
, CE
1
and
UB/LB
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
UB/LB.
6. When
REPEAT
is asserted, the counter will reset to the last valid address loaded via
ADS.
This value is not set at power-up: a known location should be loaded
via
ADS
during initialization if desired. Any subsequent
ADS
access during operations will update the
REPEAT
address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timing Waveform of Counter Repeat, page 17. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA
0L
- BA
5L
≠
BA
0R
- BA
5R
), as this condition will invalidate the access for both ports. Please refer to the functional description on page 18 for details.
6.42
5
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