64Mx64 bits
Unbuffered DDR SO-DIMM
HYMD564M646A(L)8-J/K/H
DESCRIPTION
Preliminary
Hynix HYMD564M646A(L)8-J/K/H series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline
Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix
HYMD564M646A(L)8-J/K/H series consists of eight 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin
glass-epoxy substrate. Hynix HYMD564M646A(L)8-J/K/H series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD564M646A(L)8-J/K/H series is designed for high speed of up to 166MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD564M646A(L)8-J/K/H series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
•
•
•
•
•
512MB (64M x 64) Unbuffered DDR SO-DIMM
based on 64Mx8 DDR SDRAM
JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
133MHz/166MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
•
•
•
•
•
•
•
•
Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
ORDERING INFORMATION
Part No.
HYMD564M646A(L)8-J
HYMD564M646A(L)8-K
HYMD564M646A(L)8-H
V
DD
=2.5V
V
DDQ
=2.5V
Power Supply
Clock Frequency
166MHz (*DDR333)
133MHz (*DDR266A)
133MHz (*DDR266B)
Interface
Form Pactor
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004
2
HYMD564M646A(L)8-J/K/H
FUNCTIONAL BLOCK DIAGRAM
/CS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS4
DM4
DQS
D0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D4
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS5
DM5
DQS
D1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS6
DM6
DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D6
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS7
DM7
DQS
D3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DQS
D7
Serial PD
VDDSPD
VDD/VDDQ
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
VREF
VSS
VDDID
.
=
=
.
.
.
.
.
=
..
.
SPD
D0 - D7
D0 - D7
D0 - D7
Strap:see Note 4
BA0-BA1
A0 - A12
/RAS
/CAS
CKE0
/WE
BA0-BA1 : SDRAMs D0 - D7
A0 - A12 : SDRAMs D0 - D7
/RAS : SDRAMs D0 - D7
/CAS : SDRAMs D0 - D7
CKE : SDRAMs D0 - D7
/WE : SDRAMs D0 - D7
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown
3. DQ, DQS, DM/DQS resistors : 22Ohms+/-5%
4. VDDID strap connections
(for memory device VDD, VDDQ) :
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD= VDDQ
Rev. 0.2 / Apr. 2004
4
HYMD564M646A(L)8-J/K/H
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature (Ambient)
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
1.0 x # of Components
260 / 10
Rating
o
Unit
C
o
C
V
V
V
mA
W
o
C
/ Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA= 0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
Min
2.3
2.3
V
REF
+ 0.15
-0.3
V
REF
- 0.04
1.15
Typ.
2.5
2.5
-
-
V
REF
1.25
Max
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
1.35
Unit
V
V
V
V
V
V
3
2
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA= 0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+ 0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2 / Apr. 2004
5
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