CAT5261
Dual Digitally Programmable Potentiometers
(DPP™) with 256 Taps and SPI Interface
FEATURES
Two linear-taper digitally programmable
potentiometers
256 resistor taps per potentiometer
End to end resistance 50kΩ or 100kΩ
Potentiometer control and memory access via
SPI interface
Low wiper resistance, typically 100
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The CAT5261 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 8 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the wiper
tap switches for each DPP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the non-
volatile data registers is via a SPI serial bus. On power-
up, the contents of the first data register (DR0) for each
of the potentiometers is automatically loaded into its
respective wiper control register.
The CAT5261 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC/TSSOP (W, Y)
SO
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
1
2
3
4
5
6
7
8
9
¯¯¯¯¯
24 HOLD
23 SCK
22 NC
21 NC
20 NC
FUNCTIONAL DIAGRAM
R
H0
CS
SCK
SI
SO
R
H1
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R
W0
R
W1
WP
A0
A1
HOLD
CAT
19 NC
5261
18 GND
17 R
W1
16 R
H1
15 R
L1
14 A1
13 SI
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
R
W0
10
¯¯¯ 11
CS
¯¯¯ 12
WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2122 Rev. E
CAT5261
PIN DESCRIPTIONS
SI: Serial Input
SI is the serial data input pin. This pin is used
to input all opcodes, byte addresses and data
to be written to the CAT5261. Input data is
latched on the rising edge of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is
used to transfer data out of the CAT5261.
During a read cycle, data is shifted out on the
falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5261. Opcodes,
byte addresses or data present on the SI pin
are latched on the rising edge of the SCK.
Data on the SO pin is updated on the falling
edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of four
devices can be addressed on a single bus. A
match in the slave address must be made
with the address input in order to initiate
communication with the CAT5261.
R
H
, R
L
: Resistor End Points
The R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical
potentiometer.
R
W
: Wiper
The RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
SO
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
¯¯¯
CS
¯¯¯
WP
SI
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
Function
Serial Data Output
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Supply Voltage
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
23
SCK
Bus Serial Clock
¯¯¯: Chip Select
CS
¯¯¯¯¯
24
HOLD Hold
¯¯¯ is the Chip select pin. ¯¯¯ low enables
CS
CS
the CAT5261 and ¯¯¯ high disables the
CS
¯¯¯ high takes the SO output pin to high impedance and forces the devices into a Standby mode
CAT5261. CS
(unless an internal write operation is underway). The CAT5261 draws ZERO current in the Standby mode. A high
to low transition on ¯¯¯ is required prior to any sequence being initiated. A low to high transition on ¯¯¯ after a
CS
CS
valid write sequence is what initiates an internal write cycle.
¯¯¯: Write Protect
WP
¯¯¯ is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
WP
¯¯¯ is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register
WP
is allowed). ¯¯¯ going low while ¯¯¯ is still low will interrupt a write to the registers. If the internal write cycle has
WP
CS
already been initiated, ¯¯¯ going low will have no effect on any write operation.
WP
¯¯¯¯¯
HOLD: Hold
¯¯¯¯¯
The HOLD pin is used to pause transmission to the CAT5261 while in the middle of a serial sequence without
¯¯¯¯¯
having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be
¯¯¯¯¯
¯¯¯¯¯
ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any
¯¯¯¯¯ may be tied high directly to V
CC
or tied to V
CC
through a resistor.
time this function is not being used.) HOLD
¯¯¯: Write Protect Input
WP
The ¯¯¯ pin when tied low prevents non-volatile writes to the device (change of wiper control register is allowed)
WP
and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 6 for
more details.
Doc. No. MD-2122 Rev. E
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5261
SERIAL BUS PROTOCOL
The CAT5261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5261 to interface directly with
many of today's popular microcontrollers. The
CAT5261 contains an 8-bit instruction register .The
instruction set and the operation codes are detailed in
the instruction set table 3 on page 9.
DEVICE OPERATION
The CAT5261 is two resistor arrays integrated with an
SPI serial interface logic, two 8-bit wiper control
registers and eight 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
).
R
H
and R
L
are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (R
W
) by a After the device is selected with
¯¯¯ going low the first byte will be received. The part
CS
is accessed via the SI pin, with data being clocked in
on the rising edge of SCK. The first byte contains one
of the six op-codes that define the operation to be
performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper
control register. Data can be read or written to the
wiper control registers or the non-volatile memory
data registers via the SPI bus. Additional instructions
allows data to be transferred between the wiper
control registers and each respective potentiometer's
non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2122 Rev. E
CAT5261
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground
(1) (2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25ºC)
Lead Soldering Temperature (10s)
Wiper Current
RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(5)
Relative Linearity
(6)
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
Min
Limits
Typ.
100
50
Max
Units
kΩ
kΩ
±20
25°C, each pot
I
W
= ±3mA @ V
CC
= 3V
I
W
= ±3mA @ V
CC
= 5V
0
(4)
0.4
Rw(n)(actual)-R(n)(expected)
Rw(n+1)-[Rw(n)+LSB]
(8)
(4)
(4)
(4)
R
POT
= 50kΩ
(4)
(8)
Ratings
-55 to +125
-65 to +150
-2.0 to +V
CC
+ 2.0
-0.2 to +7.0
1.0
300
±6
Ratings
+2.5 to +6.0
-40 to +85
Units
ºC
°C
V
V
W
ºC
mA
Units
V
°C
%
%
mW
mA
Ω
Ω
V
nV
√
Hz
%
LSB
(7)
LSB
(7)
ppm/ºC
ppm/ºC
pF
MHz
I
W
R
W
R
W
V
TERM
VN
200
100
1
50
±3
300
150
V
CC
±1
±0.2
±300
20
10/10/25
0.4
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = R
TOT
/ 255 or (R
H
- R
L
) / 255, single pot
(8) n = 0, 1, 2, ..., 255
Doc. No. MD-2122 Rev. E
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5261
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OH1
Parameter
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Output High Voltage
I
OL
= 3mA
I
OH
= -1.6mA
V
CC
– 0.8
Test Conditions
f
SCL
= 400kHz, SDA = Open
V
CC
= 6V, Inputs = GNDs
f
SCK
= 400kHz, SDA Open
V
CC
= 6V, Input = GND
V
IN
= GND or V
CC
, SDA = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
µA
µA
µA
V
V
V
V
Min
Max
1
5
Units
mA
mA
PIN CAPACITANCE
(1)
T
A
= 25ºC, f = 1.0MHz, V
CC
= 5V, unless otherwise specified.
Symbol
C
OUT(1)
C
IN(1)
Symbol
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
Test
Output Capacitance (SO)
Input Capacitance (¯¯¯, SCK, SI, ¯¯¯,HOLD, A0, A1)
CS
WP ¯¯¯¯¯
Parameter
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
¯¯¯¯¯
HOLD to Output Low Z
Input Rise Time
Input Fall Time
¯¯¯¯¯
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
¯¯¯¯¯
HOLD to Output High Z
¯¯¯ High Time
CS
¯¯¯ Setup Time
CS
¯¯¯ Hold Time
CS
C
L
= 50pF
Test Conditions
Conditions
V
OUT
= 0V
V
IN
= 0V
Min
50
50
125
125
DC
Max
8
6
Max
Units
pF
pF
Units
ns
ns
ns
ns
A.C. CHARACTERISTICS
3
50
2
2
MHz
ns
µs
µs
ns
ns
100
100
200
0
250
100
2
250
250
ns
ns
ns
ns
ns
ns
ns
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2122 Rev. E
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