CAT5259
Quad Digitally Programmable Potentiometers
(DPP™) with 256 Taps and I²C Interface
FEATURES
Four linear taper digitally programmable
potentiometers
256 resistor taps per potentiometer
End to end resistance 50kΩ or 100kΩ
Potentiometer control and memory access via
I²C interface
Low wiper resistance, typically 100Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The CAT5259 is four digitally programmable poten–
tiometers (DPPs™) integrated with control logic and
16 bytes of NVRAM memory. Each DPP consists of a
series of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a I²C serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers
is automatically loaded into its respective wiper
control registers.
The CAT5259 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the 0ºC to 70ºC
commercial and -40ºC to 85ºC industrial operating
temperature ranges and offered in a 24-lead SOIC
and TSSOP package.
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
NC
A0
R
W3
R
H3
R
L3
NC
V
CC
R
LO
R
HO
1
2
3
4
5
6
7
8
9
24 A3
23 SCL
22 R
L2
21 R
H2
20 R
W2
19 NC
18 GND
17 R
W1
16 R
H1
15 R
L1
14 A1
13 SDA
WP
A
0
A
1
A
2
A
3
SCL
SDA
FUNCTIONAL DIAGRAM
R
H0
R
H1
R
H2
R
H3
I²C BUS
INTERFACE
WIPER CONTROL
REGISTERS
R
W0
R
W1
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
R
W2
R
W3
R
L0
R
L1
R
L2
R
L3
R
WO
10
A2 11
¯¯¯ 12
WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2000 Rev. H
CAT5259
PIN DESCRIPTIONS
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
NC
A0
R
W3
R
H3
R
L3
NC
V
CC
R
L0
R
H0
R
W0
A2
¯¯¯
WP
SDA
A1
R
L1
R
H1
R
W1
GND
NC
R
W2
R
H2
R
L2
SCL
A3
Function
No Connect
Device Address, LSB
Wiper Terminal for Potentiometer 3
High Reference Terminal for Potentiometer 3
Low Reference Terminal for Potentiometer 3
No Connect
Supply Voltage
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
Wiper Terminal for Potentiometer 2
High Reference Terminal for Potentiometer 2
Low Reference Terminal for Potentiometer 2
Bus Serial Clock
Device Address
SCL: Serial Clock
The CAT5259 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA: Serial Data
The CAT5259 bidirectional serial data pin is
used to transfer data into and out of the device.
The SDA pin is an open drain output and can
be wire-Ored with the other open drain or open
collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate
communication with the CAT5259.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent
to the terminal connections on a mechanical
potentiometer.
R
W
: Wiper
The four R
W
pins are equivalent to the wiper
terminal of a mechanical potentiometer.
¯¯¯: Write Protect Input
WP
The ¯¯¯ pin when tied low prevents non-volatile
WP
writes to the device (change of wiper control
register is allowed) and when tied high or left
floating normal read/write operations are
allowed. See Write Protection on page 6 for
more details.
DEVICE OPERATION
The CAT5259 is four resistor arrays integrated with a I²C serial interface logic, four 8-bit wiper control registers
and sixteen 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive
elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
). The tap positions between and at the ends of the series resistors are
connected to the output wiper terminals (R
W
) by a CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control
register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via
the I²C bus. Additional instructions allow data to be transferred between the wiper control registers and each
respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an
"increment/decrement" mode.
Doc. No. MD-2000 Rev. H
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5259
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to V
SS(1) (2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25ºC)
Lead Soldering Temperature (10sec)
Wiper Current
RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (100kΩ)
Potentiometer Resistance (50kΩ)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(5)
Relative Linearity
(6)
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
Min
Limits
Typ.
100
50
Max.
Units
kΩ
kΩ
±20
25°C, each pot
I
W
= ±3mA @ V
CC
= 3V
I
W
= ±3mA @ V
CC
= 5V
V
SS
= 0V
(4)
R
W(n)(actual)
-R
(n)(expected)(8)
R
W(n+1)
-[R
W(n)+LSB
]
(8)
(4)
(4)
(4)
R
POT
= 50kΩ
(4)
±300
20
10/10/25
0.4
200
100
V
SS
0.4
±1
±0.2
1
50
+3
300
150
V
CC
%
%
mW
mA
Ω
Ω
V
nV
√
Hz
%
LSB
(7)
LSB
(7)
ppm/ºC
ppm/ºC
pF
MHz
Ratings
+2.5 to +6
-40 to +85
Units
V
°C
Ratings
-55 to +125
-65 to +150
-2.0 to +V
CC
+ 2.0
-2.0 to +7.0
1.0
300
±6
Units
ºC
°C
V
V
W
ºC
mA
I
W
R
W
R
W
V
TERM
V
N
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = R
TOT
/ 255 or (R
H
- R
L
) / 255, single pot
(8) n = 0, 1, 2, ..., 255
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2000 Rev. H
CAT5259
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400kHz, SDA = Open
V
CC
= 6V, Inputs = GND
f
SCK
= 400kHz, SDA Open
V
CC
= 6V, Input = GND
V
IN
= GND or V
CC
, SDA = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Max
1
5
5
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
µA
µA
µA
V
V
V
CAPACITANCE
T
A
= 25ºC, f = 1.0MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, ¯¯¯)
WP
Conditions
V
I/O
= 0V
V
IN
= 0V
Max.
8
6
2.5V - 6.0V
Symbol
f
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(1)
Units
pF
pF
A.C. CHARACTERISTICS
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
Min.
Max.
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
t
F(1)
t
SU:STO
t
DH
Notes:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2000 Rev. H
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5259
POWER UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Symbol
t
WRPO
t
WRL
Symbol
t
WR
Symbol
N
END(4)
T
DR
(4)
Parameter
Power-up to Read Operation
Power-up to Write Operation
Parameter
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Parameter
Write Cycle Time
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Min
5
5
Max
1
1
Max
10
10
Max
5
Max
Units
ms
ms
Units
µs
µs
Units
ms
Units
Cycles/Byte
Years
V
mA
XDCP TIMING
WRITE CYCLE LIMITS
(3)
RELIABILITY CHARACTERISTICS
V
ZAP(4)
I
LTH(4)
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
(3)
(4)
t
PUR
and t
PUW
are delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
This parameter is tested initially and after a design or process change that affects the parameter.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2000 Rev. H
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